From 0978a5d72bf809f4e64e907957c07a1d7013ad74 Mon Sep 17 00:00:00 2001
From: bacon <bacon@rtems.cn>
Date: Sat, 16 Aug 2025 18:46:19 +0800
Subject: [PATCH] =?UTF-8?q?=E8=BF=9B=E4=B8=80=E6=AD=A5=E5=8F=82=E6=95=B0?=
 =?UTF-8?q?=E5=8C=96=E4=BB=A3=E7=A0=81?=
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---
 tb/shinTest/ShinTopSpiTb.v | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index cc94de1..48deef9 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -57,7 +57,23 @@ module ShinTopSpiTb(
 `define IQSPI_CSN(id)        spi_csn[`IQSPI_CSN_NUM(`id)]
 `define ESPI_CSN(id)         spi_csn[`ESPI_CSN_NUM(`id)]
 `define EQSPI_CSN(id)        spi_csn[`EQSPI_CSN_NUM(`id)]
-
+`define QSPI_MUX_MISO_INIT    \
+    (`IQSPI_MISO(0) & ~{4{`IQSPI_CSN(0)}}) |\
+    (`IQSPI_MISO(1) & ~{4{`IQSPI_CSN(1)}}) |\
+    (`IQSPI_MISO(2) & ~{4{`IQSPI_CSN(2)}}) |\
+    (`IQSPI_MISO(3) & ~{4{`IQSPI_CSN(3)}}) |\
+    (`IQSPI_MISO(4) & ~{4{`IQSPI_CSN(4)}}) |\
+    (`EQSPI_MISO(0) & ~{4{`EQSPI_CSN(0)}}) |\
+    (`EQSPI_MISO(1) & ~{4{`EQSPI_CSN(1)}}) |\
+    (`EQSPI_MISO(2) & ~{4{`EQSPI_CSN(2)}}) |\
+    (`EQSPI_MISO(3) & ~{4{`EQSPI_CSN(3)}}) |\
+    (`EQSPI_MISO(4) & ~{4{`EQSPI_CSN(4)}})
+`define SPI_MUX_MISO_INIT     \
+    ( spi_miso[0] & ~`ESPI_CSN(0)) |\
+    ( spi_miso[1] & ~`ESPI_CSN(1)) |\
+    ( spi_miso[2] & ~`ESPI_CSN(2)) |\
+    ( spi_miso[3] & ~`ESPI_CSN(3)) |\
+    ( spi_miso[4] & ~`ESPI_CSN(4))
 
     wire [(`DEV_NUM - 1):0] dDat_w;
     wire [(`DEV_NUM - 1):0] uDat_w;
@@ -438,7 +454,7 @@ end
   assign spi_mosi = exChangeRego[7];
   assign qspi_mosi = exChangeRego[7:4];
 
-  wire [3:0] qspi_mux_miso = 
+  wire [3:0] qspi_mux_miso = `QSPI_MUX_MISO_INIT;
     //( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) |
     //( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) |
     //( qspi_miso[4*2+3:4*2] & ~{4{spi_csn[ 2]}}) |
@@ -449,6 +465,7 @@ end
     //( qspi_miso[4*7+3:4*7] & ~{4{spi_csn[12]}}) |
     //( qspi_miso[4*8+3:4*8] & ~{4{spi_csn[13]}}) |
     //( qspi_miso[4*9+3:4*9] & ~{4{spi_csn[14]}});
+    /*
     (`IQSPI_MISO(0) & ~{4{`IQSPI_CSN(0)}}) |
     (`IQSPI_MISO(1) & ~{4{`IQSPI_CSN(1)}}) |
     (`IQSPI_MISO(2) & ~{4{`IQSPI_CSN(2)}}) |
@@ -459,18 +476,21 @@ end
     (`EQSPI_MISO(2) & ~{4{`EQSPI_CSN(2)}}) |
     (`EQSPI_MISO(3) & ~{4{`EQSPI_CSN(3)}}) |
     (`EQSPI_MISO(4) & ~{4{`EQSPI_CSN(4)}});
+    */
 
-  wire spi_mux_miso = 
+  wire spi_mux_miso = `SPI_MUX_MISO_INIT;
     //( spi_miso[0] & ~spi_csn[5] ) |
     //( spi_miso[1] & ~spi_csn[6] ) |
     //( spi_miso[2] & ~spi_csn[7] ) |
     //( spi_miso[3] & ~spi_csn[8] ) |
     //( spi_miso[4] & ~spi_csn[9] );
+    /*
     ( spi_miso[0] & ~`ESPI_CSN(0)) |
     ( spi_miso[1] & ~`ESPI_CSN(1)) |
     ( spi_miso[2] & ~`ESPI_CSN(2)) |
     ( spi_miso[3] & ~`ESPI_CSN(3)) |
     ( spi_miso[4] & ~`ESPI_CSN(4));
+    */
 
   reg isReq = 0;
   reg isBusy = 0;