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合并通讯线路的交叉功能,为环网做准备

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This commit is contained in:
bacon
2025-09-01 16:18:25 +08:00
parent a5919e29c0 0bcb947a2d
commit 08f602ab1b
2 changed files with 100 additions and 28 deletions
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35
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -52,6 +52,10 @@ class CommonRegisterBundle extends Bundle{
val refTop = UInt(3.W)
val bias = UInt(2.W)
val dwupEx = UInt(16.W)
val b8b4Sel = UInt(16.W)
val cdrParam = UInt(16.W)
val softResetCode = Vec(4, UInt(8.W))
@@ -295,7 +299,20 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === ("h48".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
}) ++
((0 until 2).map{ i =>
(addr === ("h4c".U(16.W) + i.U) ) -> cReg.b8b4Sel( 8*i+7,8*i+0 )
}) ++
((0 until 2).map{ i =>
(addr === ("h4e".U(16.W) + i.U) ) -> cReg.cdrParam( 8*i+7,8*i+0 )
}) ++
Seq(
(addr === "h4a".U ) -> cReg.dwupEx.extract(0),
(addr === "h4c".U ) -> cReg.b8b4Sel.extract(0),
(addr === "h4e".U ) -> cReg.cdrParam(7,0),
(addr === "h50".U ) -> cReg.anamuxSel,
(addr === "h51".U ) -> cReg.ldo2p5,
(addr === "h52".U ) -> cReg.ldo1p1,
@@ -1087,6 +1104,24 @@ trait InterfaceSystem{ this: InterfaceBase =>
cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U )
cReg.dwupEx :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4b".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
)
cReg.b8b4Sel :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4d".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
)
cReg.cdrParam :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4f".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
)
cReg.intEnable :=
Cat(
1.U(1.W), //复位中断，时钟为1 //31 上电复位

93
src/main/scala/backBoard/shin/MstSlvSwitch.scala
View File

@@ -472,41 +472,78 @@ class MstSlvSwitch extends MstSlvSwitchBase
with MstSlvSwitchMaster
with MstSlvSwitchSlave
with MstSlvSwitchWatchDog{
val isDwUpEx = interface.io.cReg.dwupEx(15,8) === "h58".U && interface.io.cReg.dwupEx.extract(0)
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
when( ~isDwUpEx ){ //未交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.dDatOut := false.B
io.uDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := io.upCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.dDatOut := false.B
io.uDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := io.upCDROut.serDat
}
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := false.B
}
} .otherwise{ //交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := io.uDatIn
io.uDatOut := false.B
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.uDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.uDatOut := false.B
io.dDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.uDatIn
io.upCDRIn.serDat := io.dDatIn
io.dDatOut := io.upCDROut.serDat
io.uDatOut := io.downCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.dDatIn
io.uDatOut := io.downCDROut.serDat
io.dDatOut := false.B
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := false.B
}
}