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Revert "放弃当拍握手策略"

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This reverts commit 9c953d8963.
This commit is contained in:
RuigeLee
2024-11-01 16:01:39 +08:00
parent 9c953d8963
commit 08afdee8e3
3 changed files with 21 additions and 47 deletions
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8
src/main/scala/backBoard/pico/BackSystem.scala
View File

@@ -159,21 +159,21 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b10".U & ~pico.io.mem.instr
pico.io.mem.ready :=
// Mux( pico.io.mem.instr, sram.io.mem.ready,
Mux( pico.io.mem.instr, sram.io.mem.ready,
Mux1H(Seq(
(pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.ready,
(pico.io.mem.addr(13,12) === "b01".U ) -> cdr.io.mem.ready,
(pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.ready,
))
// )
)
pico.io.mem.rdata :=
// Mux( pico.io.mem.instr, sram.io.mem.rdata,
Mux( pico.io.mem.instr, sram.io.mem.rdata,
Mux1H(Seq(
(pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.rdata,
(pico.io.mem.addr(13,12) === "b01".U ) -> cdr.io.mem.rdata,
(pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.rdata,
))
// )
)
sram.io.mem.wdata := pico.io.mem.wdata
cdr.io.mem.wdata := pico.io.mem.wdata

12
src/main/scala/backBoard/pico/SimpleSRAM.scala
View File

@@ -41,14 +41,16 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
// } .otherwise { io.mem.rdata := Cat( mem(io.mem.addr(11,2)).reverse ) }
// }
val isAck = RegInit(false.B)
val isReadAck = RegInit(false.B)
when( io.mem.fire ){
isAck := false.B
} .elsewhen( io.mem.valid & ~isAck ){
isAck := true.B
isReadAck := false.B
} .elsewhen( io.mem.valid & io.mem.wstrb === 0.U ){
isReadAck := true.B
}
io.mem.ready := isAck
io.mem.ready :=
( io.mem.wstrb =/= 0.U & true.B ) |
( io.mem.wstrb === 0.U & isReadAck )

48
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -191,7 +191,7 @@ trait TLCDRRx{ this: TLCDRBase =>
rxFifo.reset := reset.asBool | isTLWriteSoftReset
// rxFifo.io.deq.ready := isTLReadRxFifo
rxFifo.io.deq.ready := isTLReadRxFifo
when( isTLWriteSoftReset ){
@@ -217,37 +217,9 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
dirSel := io.mem.wdata
}
val isAck = RegInit(false.B)
val rdata = Reg(UInt(32.W))
when( io.mem.fire ){
isAck := false.B
} .elsewhen( io.mem.valid & ~isAck ){
when( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready ){
isAck := true.B
} .otherwise{
when( io.mem.addr(4,0) === "h1c".U & rxFifo.io.deq.valid ){
isAck := true.B
rdata := rxFifo.io.deq.bits
} .elsewhen( io.mem.addr(4,0) === "h18".U ){
isAck := true.B
rdata := rxLen
} .elsewhen( io.mem.addr(4,0) === "h0".U ){
isAck := true.B
rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError)
}
}
}
rxFifo.io.deq.ready := io.mem.valid & ~isAck & io.mem.addr(4,0) === "h1c".U & rxFifo.io.deq.valid
io.mem.ready := isAck
// ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
// ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
io.mem.ready :=
( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
@@ -257,12 +229,12 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
io.interrupt(3) := intRxEnd
io.mem.rdata := rdata
// Mux1H(Seq(
// isTLReadStatus -> ,
// isTLReadRxLen -> rxLen,
// isTLReadRxFifo -> rxFifo.io.deq.bits
// ))
io.mem.rdata :=
Mux1H(Seq(
isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError),
isTLReadRxLen -> rxLen,
isTLReadRxFifo -> rxFifo.io.deq.bits
))