ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

更新软件代码

Browse Source
This commit is contained in:
Ruige Lee
2025-01-15 11:44:30 +08:00
parent f12bc41c52
commit 074321ae58
8 changed files with 49 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
tb/sw/src/MstMain.c
View File

@@ -3,22 +3,7 @@
// #include "uart.h"
// #include "gpio.h"
// #include "timer.h"
#include "custom_ops.S"
volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
volatile uint32_t *cdr_txLen = (uint32_t*)( 0x000 + 0x4 ); //write
volatile uint32_t *cdr_txFifo = (uint32_t*)( 0x000 + 0x8 ); //write
volatile uint32_t *cdr_direct = (uint32_t*)( 0x000 + 0xc ); //write
volatile uint32_t *cdr_softReset = (uint32_t*)( 0x000 + 0x10 ); //write
volatile uint32_t *cdr_rxLen = (uint32_t*)( 0x000 + 0x18 ); //read
volatile uint32_t *cdr_rxFifo = (uint32_t*)( 0x000 + 0x1c ); //read
volatile uint32_t *WriteGpio = (uint32_t*) ( 0x400);
volatile uint32_t *ReadGpio = (uint32_t*) ( 0x400);
volatile uint32_t *ReadIsLast = (uint32_t*) ( 0x408);
#include "tl2cdr.h"
@@ -31,6 +16,13 @@ static inline void error() {
}
// extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
// extern volatile uint32_t *cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
// extern volatile uint32_t *cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
// extern volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
// extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
// extern volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
// extern volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
@@ -48,13 +40,6 @@ void main()
uint32_t led = 0;
asm volatile (
"li sp, 0\n"
".4byte 0x600600b\n"
);
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 0;
@@ -82,14 +67,13 @@ void main()
//发送下行包头
*cdr_txLen = 520; //总长520
*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x5a5a; //负载长度512，操作数0， 参数全0//测试，防止脱锁
*cdr_txFifo = 0x5a5a5a5a; //测试，防止脱锁
*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x0000; //负载长度512，操作数0， 参数全0
*cdr_txFifo = 0x00000000;
for( uint32_t i = 0; i < 512/4; i ++ ){
*cdr_txFifo = 0xaa5555aa;//测试，防止脱锁
*cdr_txFifo = 0x00000000;
}
//等待发送完成标志
asm volatile (
"1:\n"

0
tb/sw/src/custom_ops.S → tb/sw/src/custom_ops.S.bk
View File

0
tb/sw/src/mstMain.S → tb/sw/src/mstMain.S.bk
View File

28
tb/sw/src/mstStartup.S
View File

@@ -9,8 +9,7 @@
_prog_start:
li sp, 0
picorv32_maskirq_insn(zero, zero)
li sp, 0x40001000
call main
ecall
@@ -21,34 +20,13 @@ _prog_start:
.balign 32
.section .trap_entry, "ax", %progbits
trap_entry:
# q0 return address
# q1 bitmask of all IRQ to be handled, may be more than one IRQ
# q2 q3 unused, can be use as temp storage register
# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
# addi x15, x4, 0
or sp, sp, x4
picorv32_retirq_insn()

19
tb/sw/src/slvStartup.S
View File

@@ -9,23 +9,16 @@
_prog_start:
li sp, 0
picorv32_maskirq_insn(zero, zero)
li sp, 0x40001000
call main
ecall
.balign 32
.section .trap_entry, "ax", %progbits
trap_entry:
# q0 return address
# q1 bitmask of all IRQ to be handled, may be more than one IRQ
# q2 q3 unused, can be use as temp storage register
# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
# io.interrupt(0) := intTxError
# io.interrupt(1) := intRxError
@@ -33,15 +26,5 @@ trap_entry:
# io.interrupt(3) := intRxEnd
or sp, sp, x4
andi x4, x4, 0x2
beqz x4, 1f
li x4, 0
sw x3, 0x400(x0)
1:
picorv32_retirq_insn()

9
tb/sw/tl2cdr/tl2cdr.c
View File

@@ -72,18 +72,15 @@ uint32_t cdr_check_rx_fail(){
}
void cdr_simple_rx(uint32_t* rxLen, uint8_t* operator, uint8_t* data){
uint32_t readDat;
readDat = *cdr_rxFifo;
&operator = (readDat >> 16) & 0xf;
&rxLen = readDat >> 20;
readDat = *cdr_rxFifo;
for( uint32_t i = 0; i < (&rxLen >> 2); i ++ ){ //一次传4byte
readDat = *cdr_rxFifo;
data[4*i+1] = (uint8_t)( (readDat >> 0) & 0xFF);
@@ -98,6 +95,10 @@ void cdr_simple_rx(uint32_t* rxLen, uint8_t* operator, uint8_t* data){
}
void cdr_slave_function(){
}

8
tb/sw/tl2cdr/tl2cdr.h
View File

@@ -23,7 +23,13 @@
#define CDR_ReadRxLen 0x18
#define CDR_ReadRxFifo 0x1c
extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
extern volatile uint32_t *cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
extern volatile uint32_t *cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
extern volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
extern volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
extern volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
// extern uint8_t gpio_read();
// extern uint32_t gpio_write( uint32_t data );

22
tb/verilator/SimTop.v
View File

@@ -327,6 +327,8 @@ string testName;
reg [7:0] mem0 [0:200000];
reg [7:0] mem1 [0:200000];
reg [7:0] mem2 [0:200000];
reg [7:0] mem3 [0:200000];
localparam DP = 8192;
integer i;
@@ -367,6 +369,26 @@ initial begin
end
end
$readmemh("./tb/sw/build/slvTest.verilog", mem2);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
`MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
end
else begin
`MEM2[i] = 32'h0;
end
end
$readmemh("./tb/sw/build/slvTest.verilog", mem3);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
`MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
end
else begin
`MEM3[i] = 32'h0;
end
end
end