ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

更新软件代码

Browse Source
This commit is contained in:
Ruige Lee
2025-01-15 11:44:30 +08:00
parent f12bc41c52
commit 074321ae58
8 changed files with 49 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
tb/verilator/SimTop.v
View File

@@ -327,6 +327,8 @@ string testName;
reg [7:0] mem0 [0:200000];
reg [7:0] mem1 [0:200000];
reg [7:0] mem2 [0:200000];
reg [7:0] mem3 [0:200000];
localparam DP = 8192;
integer i;
@@ -367,6 +369,26 @@ initial begin
end
end
$readmemh("./tb/sw/build/slvTest.verilog", mem2);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
`MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
end
else begin
`MEM2[i] = 32'h0;
end
end
$readmemh("./tb/sw/build/slvTest.verilog", mem3);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
`MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
end
else begin
`MEM3[i] = 32'h0;
end
end
end