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高云FPGA：dout新检测特性；删除退役的版本

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This commit is contained in:
Ruige Lee
2025-03-12 17:36:10 +08:00
parent 1da2747d44
commit 0612a99da2
6 changed files with 90 additions and 377 deletions
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5
Makefile
View File

@@ -31,9 +31,8 @@ back:
cp ./src/main/verilog/backBoardMstTop.v ./generated/back/ cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
cp ./src/main/verilog/oser_rst.v ./generated/back/ cp ./src/main/verilog/oser_rst.v ./generated/back/
cp ./src/main/verilog/di16_top.v ./generated/back/ cp ./src/main/verilog/di16_top.v ./generated/back/
cp ./src/main/verilog/do16_top.v ./generated/back/ cp ./src/main/verilog/do16c_top.v ./generated/back/
cp ./src/main/verilog/do16inv_top.v ./generated/back/ cp ./src/main/verilog/do16p_top.v ./generated/back/
cp ./src/main/verilog/qei_top.v ./generated/back/
cp ./src/main/verilog/spi_top.v ./generated/back/ cp ./src/main/verilog/spi_top.v ./generated/back/
cp ./src/main/verilog/defineParam.v ./generated/back/ cp ./src/main/verilog/defineParam.v ./generated/back/

80
src/main/scala/backBoard/Dout16.scala
View File

@@ -18,17 +18,72 @@ trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
} }
trait DoutInspect{ this: BackBoardSlvLocal =>
class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
val flt = IO(Input(Vec(2, Bool()))) val flt = IO(Input(Vec(2, Bool())))
val v24Det = IO(Input(Bool())) val v24Det = IO(Input(Bool()))
val LED_ERR = IO(Output(Bool())) val LED_ERR = IO(Output(Bool()))
val outReg = RegInit(0.U(16.W))
LED_ERR := v24Det LED_ERR := ~RegNext(~v24Det)
when( statusPage === 0.U ){
upReg(2) := Cat( 0.U(7.W), RegNext(~v24Det) )
upReg(3) := 0.U
upReg(4) := Cat( 0.U(7.W), RegNext(~flt(0)) )
upReg(5) := 0.U
upReg(6) := Cat( 0.U(7.W), RegNext(~flt(1)) )
upReg(7) := 0.U
}
}
trait DoutInspect_Plus{ this: BackBoardSlvLocal =>
val flashCounter: UInt
val v24Det = IO(Input(Bool()))
val LED_ERR = IO(Output(Bool()))
val fin_cur = IO(Input(UInt(4.W)))
val fin_sel = IO(Output(UInt(3.W)))
val fin_clk = IO(Output(Bool()))
val fin_vol = IO(Input(UInt(3.W)))
val inspectCurr = for( i <- 0 until 4 ) yield { RegInit(0.U(8.W)) }
val finSelReg = RegInit(0.U(3.W)); fin_sel := finSelReg
val finClkReg = RegInit(false.B); fin_clk := finClkReg
when(flashCounter(2,0).andR){
finClkReg := ~finClkReg
}
when( flashCounter(2,0).andR & finClkReg ){
finSelReg := finSelReg + 1.U
inspectCurr(0) := ( inspectCurr(0) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(0) << finSelReg )
inspectCurr(1) := ( inspectCurr(1) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(1) << finSelReg )
inspectCurr(2) := ( inspectCurr(2) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(2) << finSelReg )
inspectCurr(3) := ( inspectCurr(3) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(3) << finSelReg )
}
LED_ERR := ~( RegNext(~v24Det) | ( inspectCurr.map{ (isp: UInt) => (isp =/= 0.U) }.reduce(_|_) ) | ( RegNext(fin_vol) =/= 0.U ) )
when( statusPage === 0.U ){
upReg(2) := Cat( 0.U(4.W), RegNext(fin_vol), RegNext(~v24Det) )
upReg(3) := 0.U
upReg(4) := inspectCurr(0)
upReg(5) := inspectCurr(1)
upReg(6) := inspectCurr(2)
upReg(7) := inspectCurr(3)
}
}
abstract class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
val outReg = RegInit(0.U(16.W))
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(13), downRegTemp(12)) outReg := Cat(downRegTemp(13), downRegTemp(12))
@@ -41,13 +96,6 @@ with BackBoardSlvOut16{
outRegSync := RegEnable( outReg, 0.U, isUpdate ) outRegSync := RegEnable( outReg, 0.U, isUpdate )
when( statusPage === 0.U ){ when( statusPage === 0.U ){
upReg(2) := Cat( 0.U(7.W), ~v24Det )
upReg(3) := 0.U
upReg(4) := Cat( 0.U(7.W), ~flt(0) )
upReg(5) := 0.U
upReg(6) := Cat( 0.U(7.W), ~flt(1) )
upReg(7) := 0.U
upReg(8) := mthodReg(7,0) upReg(8) := mthodReg(7,0)
upReg(9) := mthodReg(15,8) upReg(9) := mthodReg(15,8)
@@ -56,10 +104,12 @@ with BackBoardSlvOut16{
upReg(12) := outReg(7,0) upReg(12) := outReg(7,0)
upReg(13) := outReg(15,8) upReg(13) := outReg(15,8)
} }
out := outPin out := outPin
} }
class DOut16c extends DOut16 with DoutInspect
class DOut16p extends DOut16 with DoutInspect_Plus

4
src/main/verilog/do16_top.v → src/main/verilog/do16c_top.v
View File

@@ -1,6 +1,6 @@
module do16_top( module do16c_top(
input clock, input clock,
@@ -284,7 +284,7 @@ lvds_bus_slave_top i_lvds_bus_slave(
); );
DOut16 i_dout16( DOut16c i_dout16(
.reset(~resetn), .reset(~resetn),
.clock(clk_10m_a), .clock(clk_10m_a),

32
src/main/verilog/do16inv_top.v → src/main/verilog/do16p_top.v
View File

@@ -1,4 +1,6 @@
module do16_top(
module do16p_top(
input clock, input clock,
@@ -20,10 +22,11 @@ module do16_top(
output LED_PR, output LED_PR,
output LED_ERR, output LED_ERR,
output [15:0] out, output [15:0] out,
input flt_0, input v24Det,
input flt_1, input [3:0] fin_cur,
input v24Det output [2:0] fin_sel,
output fin_clk,
input [2:0] fin_vol
); );
@@ -281,10 +284,8 @@ lvds_bus_slave_top i_lvds_bus_slave(
.test_upstream_tx_10b_data() .test_upstream_tx_10b_data()
); );
wire [15:0] outInv;
assign out = ~outInv;
DOut16 i_dout16( DOut16p i_dout16(
.reset(~resetn), .reset(~resetn),
.clock(clk_10m_a), .clock(clk_10m_a),
@@ -304,13 +305,16 @@ DOut16 i_dout16(
.param_moduleID(`MODULEID), .param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION), .param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION), .param_swVersion(`SWVERSION),
.param_serial(`SERIAL), .param_serial(`SERIAL),
.LED_PR(LED_PR), .LED_PR(LED_PR),
.LED_ERR(LED_ERR), .LED_ERR(LED_ERR),
.out(outInv), .out(out),
.flt_0(flt_0),
.flt_1(flt_1),
.v24Det(v24Det), .v24Det(v24Det),
.fin_cur(fin_cur),
.fin_sel(fin_sel),
.fin_clk(fin_clk),
.fin_vol(fin_vol),
.io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out), .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
.io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid), .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),
@@ -322,6 +326,8 @@ DOut16 i_dout16(
.io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err) .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err)
); );
endmodule endmodule

342
src/main/verilog/qei_top.v
View File

@@ -1,342 +0,0 @@
module qei_top(
input clock,
input lvds_up_din_p,
input lvds_up_din_n,
output lvds_up_dout_p,
output lvds_up_dout_n,
input lvds_down_din_p,
input lvds_down_din_n,
output lvds_down_dout_p,
output lvds_down_dout_n,
output isOnline,
input isLast,
input DCIn,
output LED_PR,
input phaseAIO_0,
input phaseAIO_1,
input phaseBIO_0,
input phaseBIO_1,
input phaseZIO_0,
input phaseZIO_1
);
wire clk_400m;
wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;
wire lock_o;
wire reset_stop;
wire reset_calib;
reg rst_n;
reg rstn_d;
wire resetn;
reg resetn1=1'b1;
wire timeout_rst;
reg timeout_rst_d1;
reg timeout_rst_d2;
reg timeout_rst_d3;
reg timeout_rst_d4;
reg timeout_rst_d5;
reg timeout_rst_d6;
reg timeout_rst_d7;
reg timeout_rst_d8;
reg [3:0] resetCnt = 4'd0;
always @( posedge clock ) begin
if( resetCnt != 4'd15 ) begin
resetCnt <= resetCnt + 4'd1;
end
end
assign resetn = resetCnt == 4'd15;
always@(posedge clock or negedge resetn) begin
if(!resetn) begin
timeout_rst_d1 <= 0;
timeout_rst_d2 <= 0;
timeout_rst_d3 <= 0;
timeout_rst_d4 <= 0;
timeout_rst_d5 <= 0;
timeout_rst_d6 <= 0;
timeout_rst_d7 <= 0;
timeout_rst_d8 <= 0;
end
else begin
timeout_rst_d1 <= timeout_rst;
timeout_rst_d2 <= timeout_rst_d1;
timeout_rst_d3 <= timeout_rst_d2;
timeout_rst_d4 <= timeout_rst_d3;
timeout_rst_d5 <= timeout_rst_d4;
timeout_rst_d6 <= timeout_rst_d5;
timeout_rst_d7 <= timeout_rst_d6;
timeout_rst_d8 <= timeout_rst_d7;
end
end
always @(posedge clock or negedge resetn) begin
if(!resetn) begin
resetn1 <= 1'b1;
end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin
resetn1 <= 1'b0;
end else begin
resetn1 <= 1'b1;
end
end
reg [5:0] delay_io_last=6'b111111;
reg [15:0] counter0=0;
reg clk_en0;
wire isLast_temp;
wire isLast_temp1;
always @(posedge clk_10m_a or negedge resetn) begin
if(!resetn) begin
counter0 <= 16'd0;
clk_en0 <= 1'b0;
end else if(counter0 == 16'd9999) begin
counter0 <= 16'd0;
clk_en0 <= 1'b1;
end else begin
counter0 <= counter0 + 1;
clk_en0 <= 1'b0;
end
end
always @(posedge clk_10m_a or negedge resetn) begin
if(!resetn) begin
delay_io_last <= 6'b111111;
end else if(clk_en0 == 1'b1) begin
delay_io_last[5:1] <= delay_io_last[4:0];
delay_io_last[0] <= isLast;
end
end
assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]};
assign isLast_temp1 = ~isLast_temp;
Gowin_PLLO Gowin_PLLO(
.lock(lock_o),
.clkouta(clk_400m),
.clkin(clock)
);
wire lvds_down_din;
wire lvds_down_dout;
wire lvds_up_din;
wire lvds_up_dout;
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
.OB(lvds_down_dout_n),
.I(lvds_down_dout)
);
TLVDS_IBUF lvds_downstream_in(
.O(lvds_down_din),
.I(lvds_down_din_p),
.IB(lvds_down_din_n)
);
TLVDS_OBUF lvds_upstream_out(
.O(lvds_up_dout_p),
.OB(lvds_up_dout_n),
.I(lvds_up_dout)
);
TLVDS_IBUF lvds_upstream_in(
.O(lvds_up_din),
.I(lvds_up_din_p),
.IB(lvds_up_din_n)
);
DHCEN dhcen_inst2 (
.CLKIN(clk_400m),
.CE(reset_stop),
.CLKOUT(clk_400m_a)
);
//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
.rst_n(resetn && resetn1),
.pll_lock(lock_o), // trigged by PLL Lock
.reset_stop(reset_stop), // for DHCEN CE
.reset_calib(reset_calib), // for IDES and CLKDIV reset
.set_calib(),
.ready()
);
defparam Inst4_CLKDIVC.DIV_MODE="4";
defparam Inst4_CLKDIVC.GSREN="false";
CLKDIV Inst4_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_400m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_100m_a)
);
defparam Inst2_CLKDIVC.DIV_MODE="2";
defparam Inst2_CLKDIVC.GSREN="false";
CLKDIV Inst2_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_100m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_50m_a)
);
defparam Inst5_CLKDIVC.DIV_MODE="5";
defparam Inst5_CLKDIVC.GSREN="false";
CLKDIV Inst5_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_50m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_10m_a)
);
wire [7:0] downstream_rx_data_out;
wire downstream_rx_data_valid;
wire downstream_rx_crc_valid;
wire downstream_rx_crc_err;
wire upstream_tx_data_ready;
wire [7:0] upstream_tx_data_in;
wire downstream_rx_cdr_err;
wire upstream_rx_cdr_err;
lvds_bus_slave_top i_lvds_bus_slave(
.rst_n(resetn && resetn1),
.reset_calib(reset_calib),
.oser_pclk(clk_10m_a),
.oser_fclk(clk_50m_a),
.ides_pclk(clk_100m_a),
.ides_fclk(clk_400m_a),
.timeout_rst(timeout_rst), //add 240523
.lvds_down_din(lvds_down_din),
.lvds_down_dout(lvds_down_dout),
.lvds_up_din(lvds_up_din),
.lvds_up_dout(lvds_up_dout),
.downstream_rx_data_valid(downstream_rx_data_valid),
.downstream_rx_unicast_pkg_valid(),
.downstream_rx_data_out(downstream_rx_data_out),
.downstream_rx_crc_valid(downstream_rx_crc_valid),
.downstream_rx_crc_err(downstream_rx_crc_err),
.downstream_rx_crc_err_counter(),
.downstream_rx_cdr_err(downstream_rx_cdr_err),
.downstream_sync(),
.upstream_tx_data_ready(upstream_tx_data_ready),
.upstream_tx_unicast_pkg_ready(),
.upstream_tx_data_in(upstream_tx_data_in),
.upstream_rx_crc_valid(),
.upstream_rx_crc_err(),
.upstream_rx_crc_err_counter(),
.upstream_rx_cdr_err(upstream_rx_cdr_err),
.local_slave_id(),
.test_downstream_rx_10b_data(),
.test_downstream_rx_8b_data(),
.test_downstream_rx_state_machine(),
.test_downstream_tx_en(),
.test_downstream_tx_8b_data(),
.test_downstream_tx_10b_data(),
.test_upstream_rx_10b_data(),
.test_upstream_rx_8b_data(),
.test_upstream_rx_state_machine(),
.test_upstream_tx_en(),
.test_upstream_tx_8b_data(),
.test_upstream_tx_10b_data()
);
Qei i_qei(
.reset(~resetn),
.clock(clk_10m_a),
.io_isOnline(isOnline),
.io_isLast(isLast_temp1),
.io_DCIn(DCIn),
.io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
.io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),
.io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid),
.io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err),
.io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready),
.io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in),
.io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
.io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err),
.param_data2(`DATA2),
.param_data3(`DATA3),
.param_data4(`DATA4),
.param_data5(`DATA5),
.param_data6(`DATA6),
.param_data7(`DATA7),
.param_data8(`DATA8),
.param_data9(`DATA9),
.param_vendorID(`VENDORID),
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION),
.param_serial(`SERIAL),
.LED_PR(LED_PR),
.phaseAIO_0(phaseAIO_0),
.phaseAIO_1(phaseAIO_1),
.phaseBIO_0(phaseBIO_0),
.phaseBIO_1(phaseBIO_1),
.phaseZIO_0(phaseZIO_0),
.phaseZIO_1(phaseZIO_1)
);
endmodule

4
src/test/scala/gcd/test.scala
View File

@@ -26,11 +26,11 @@ object testModule extends App {
)) ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DOut16 }) ChiselGeneratorAnnotation(() => { new DOut16c })
)) ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new Qei }) ChiselGeneratorAnnotation(() => { new DOut16p })
)) ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq( (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(