高云FPGA：dout新检测特性；删除退役的版本

2025-03-12 17:36:10 +08:00
parent 1da2747d44
commit 0612a99da2
6 changed files with 90 additions and 377 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -26,11 +26,11 @@ object testModule extends App {
    ))

  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new DOut16 })
+      ChiselGeneratorAnnotation(() => { new DOut16c })
    ))

  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new Qei })
+      ChiselGeneratorAnnotation(() => { new DOut16p })
    ))

   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(