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高云FPGA：dout新检测特性；删除退役的版本

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This commit is contained in:
Ruige Lee
2025-03-12 17:36:10 +08:00
parent 1da2747d44
commit 0612a99da2
6 changed files with 90 additions and 377 deletions
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80
src/main/scala/backBoard/Dout16.scala
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@@ -18,17 +18,72 @@ trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
}
class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
trait DoutInspect{ this: BackBoardSlvLocal =>
val flt = IO(Input(Vec(2, Bool())))
val v24Det = IO(Input(Bool()))
val LED_ERR = IO(Output(Bool()))
val outReg = RegInit(0.U(16.W))
LED_ERR := v24Det
LED_ERR := ~RegNext(~v24Det)
when( statusPage === 0.U ){
upReg(2) := Cat( 0.U(7.W), RegNext(~v24Det) )
upReg(3) := 0.U
upReg(4) := Cat( 0.U(7.W), RegNext(~flt(0)) )
upReg(5) := 0.U
upReg(6) := Cat( 0.U(7.W), RegNext(~flt(1)) )
upReg(7) := 0.U
}
}
trait DoutInspect_Plus{ this: BackBoardSlvLocal =>
val flashCounter: UInt
val v24Det = IO(Input(Bool()))
val LED_ERR = IO(Output(Bool()))
val fin_cur = IO(Input(UInt(4.W)))
val fin_sel = IO(Output(UInt(3.W)))
val fin_clk = IO(Output(Bool()))
val fin_vol = IO(Input(UInt(3.W)))
val inspectCurr = for( i <- 0 until 4 ) yield { RegInit(0.U(8.W)) }
val finSelReg = RegInit(0.U(3.W)); fin_sel := finSelReg
val finClkReg = RegInit(false.B); fin_clk := finClkReg
when(flashCounter(2,0).andR){
finClkReg := ~finClkReg
}
when( flashCounter(2,0).andR & finClkReg ){
finSelReg := finSelReg + 1.U
inspectCurr(0) := ( inspectCurr(0) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(0) << finSelReg )
inspectCurr(1) := ( inspectCurr(1) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(1) << finSelReg )
inspectCurr(2) := ( inspectCurr(2) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(2) << finSelReg )
inspectCurr(3) := ( inspectCurr(3) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(3) << finSelReg )
}
LED_ERR := ~( RegNext(~v24Det) | ( inspectCurr.map{ (isp: UInt) => (isp =/= 0.U) }.reduce(_|_) ) | ( RegNext(fin_vol) =/= 0.U ) )
when( statusPage === 0.U ){
upReg(2) := Cat( 0.U(4.W), RegNext(fin_vol), RegNext(~v24Det) )
upReg(3) := 0.U
upReg(4) := inspectCurr(0)
upReg(5) := inspectCurr(1)
upReg(6) := inspectCurr(2)
upReg(7) := inspectCurr(3)
}
}
abstract class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
val outReg = RegInit(0.U(16.W))
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(13), downRegTemp(12))
@@ -41,13 +96,6 @@ with BackBoardSlvOut16{
outRegSync := RegEnable( outReg, 0.U, isUpdate )
when( statusPage === 0.U ){
upReg(2) := Cat( 0.U(7.W), ~v24Det )
upReg(3) := 0.U
upReg(4) := Cat( 0.U(7.W), ~flt(0) )
upReg(5) := 0.U
upReg(6) := Cat( 0.U(7.W), ~flt(1) )
upReg(7) := 0.U
upReg(8) := mthodReg(7,0)
upReg(9) := mthodReg(15,8)
@@ -56,10 +104,12 @@ with BackBoardSlvOut16{
upReg(12) := outReg(7,0)
upReg(13) := outReg(15,8)
}
out := outPin
}
class DOut16c extends DOut16 with DoutInspect
class DOut16p extends DOut16 with DoutInspect_Plus