高云FPGA：dout新检测特性；删除退役的版本

Makefile

@@ -31,9 +31,8 @@ back:
 	cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
 	cp ./src/main/verilog/oser_rst.v ./generated/back/
 	cp ./src/main/verilog/di16_top.v ./generated/back/
-	cp ./src/main/verilog/do16_top.v ./generated/back/
-	cp ./src/main/verilog/do16inv_top.v ./generated/back/
-	cp ./src/main/verilog/qei_top.v ./generated/back/
+	cp ./src/main/verilog/do16c_top.v ./generated/back/
+	cp ./src/main/verilog/do16p_top.v ./generated/back/
 	cp ./src/main/verilog/spi_top.v ./generated/back/
 	cp ./src/main/verilog/defineParam.v ./generated/back/