From 05d88da3ee0187690dfa577a65da8bf0dc8c1ac5 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 9 Oct 2025 11:30:56 +0800 Subject: [PATCH] =?UTF-8?q?=E7=9C=8B=E9=97=A8=E7=8B=970=20=E5=8F=91?= =?UTF-8?q?=E9=80=81=E5=A7=8B=E8=87=B3=E6=8E=A5=E6=94=B6=E7=BB=88=20->?= =?UTF-8?q?=E5=8F=91=E9=80=81=E7=BB=88=E8=87=B3=E6=8E=A5=E6=94=B6=E5=A7=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/MstSlvSwitch.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 51879e0..ce2357f 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -484,12 +484,12 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => val wdtRec2RtnCnt = RegInit(0.U(32.W)) when( - (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) || + (upCDRInAxis.io.axis.fire & isWdtRec2RtnEnable === true.B) || ~interface.io.cReg.wdtEnable.extract(0) || interface.io.wdtTrigger(0) ){ isWdtRec2RtnEnable := false.B - } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ + } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast & interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := true.B }