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merge mirror read/write

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This commit is contained in:
RuigeLee
2023-09-08 18:47:13 +08:00
parent bf835014bc
commit 05a905ac39
2 changed files with 29 additions and 7 deletions
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13
src/main/scala/backBoard/BackBoardMst.scala
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@@ -8,7 +8,7 @@ import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
val addr = Input(UInt(11.W))
val addr = Input(UInt(10.W))
val dataIn = Input(UInt(16.W))
val dataOut = Output(UInt(16.W))
val dataOEn = Output(Bool())
@@ -71,18 +71,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
io.FSMC.dataOEn := io.FSMC.oen
val isWriteSRAM = ~fsmcAddrSync.extract(10) & fsmcAddrSync.extract(9)
val isReadSRAM = ~fsmcAddrSync.extract(10) & ~fsmcAddrSync.extract(9)
val isAccessReg = fsmcAddrSync.extract(10)
val activeAddr = fsmcAddrSync(8,0)
val isAccessSRAM = ~fsmcAddrSync.extract(9)
val isAccessReg = fsmcAddrSync.extract(9)
val activeAddr = fsmcAddrSync(8,0)
val regOut = Wire(UInt(16.W))
mirrorDown.io.enw := (~fsmcCEnSync & isWriteSRAM & (~fsmcWEnSync) )
mirrorDown.io.enw := (~fsmcCEnSync & isAccessSRAM & (~fsmcWEnSync) )
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := fsmcdataInSync
mirrorUp.io.enr := (~fsmcCEnSync & isReadSRAM & (~fsmcOEnSync) )
mirrorUp.io.enr := (~fsmcCEnSync & isAccessSRAM & (~fsmcOEnSync) )
mirrorUp.io.addrr := activeAddr