top layer and some bugs fixed
This commit is contained in:
RuigeLee
@@ -1,17 +1,715 @@
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package MAC
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import chisel3._
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import chisel3.util
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
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def isTileLink = false
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class MACBase extends Module {
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// val chipLinkMasterNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
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// managers = Seq(TLSlaveParameters.v1(
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// address = Seq(AddressSet(0x00000000L, 0x0FFFL)),
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// regionType = RegionType.UNCACHED,
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// executable = false,
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// supportsGet = TransferSizes(32/8, 32/8),
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// supportsPutFull = TransferSizes(32/8, 32/8),
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// supportsPutPartial = TransferSizes(32/8, 32/8)
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class MACIO extends Bundle{
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// )),
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// beatBytes = 32/8)))
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lazy val module = new MacImp(this)
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}
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}
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trait MacWishboneMasterIO{ this: Bundle =>
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val m_wb_adr_o = Output(UInt(32.W))
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val m_wb_sel_o = Output(UInt(4.W))
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val m_wb_we_o = Output(Bool())
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val m_wb_dat_i = Input(UInt(32.W))
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val m_wb_dat_o = Output(UInt(32.W))
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val m_wb_cyc_o = Output(Bool())
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val m_wb_stb_o = Output(Bool())
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val m_wb_ack_i = Input(Bool())
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val m_wb_err_i = Input(Bool())
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val m_wb_cti_o = Output(UInt(3.W))
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val m_wb_bte_o = Output(UInt(2.W))
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}
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trait MacWishboneSlaveIO{ this: Bundle =>
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val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input
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val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output
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val WB_ADR_I = Input(UInt(12.W)) // WISHBONE address input
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val WB_WE_I = Input(Bool()) // WISHBONE write enable input
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val WB_SEL_I = Input(UInt(4.W)) // WISHBONE byte select input
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val WB_CYC_I = Input(Bool()) // WISHBONE cycle input
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val WB_STB_I = Input(Bool()) // WISHBONE strobe input
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val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output
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val WB_ERR_O = Output(Bool()) // WISHBONE error output
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}
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class MacIO extends Bundle{
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// Tx
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val mtx_clk_pad_i = Input(Bool())
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val mtxd_pad_o = Output(UInt(4.W))
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val mtxen_pad_o = Output(Bool())
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val mtxerr_pad_o = Output(Bool())
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// Rx
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val mrx_clk_pad_i = Input(Bool())
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val mrxd_pad_i = Input(UInt(4.W))
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val mrxdv_pad_i = Input(Bool())
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val mrxerr_pad_i = Input(Bool())
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// Common Tx and Rx
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val mcoll_pad_i = Input(Bool())
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val mcrs_pad_i = Input(Bool())
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val int_o = Output(Bool())
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}
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class MacImp(outer: Mac) extends LazyModuleImp(outer){
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def isTileLink = false
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val io = IO(new MacIO with MDIO with MacWishboneMasterIO with MacWishboneSlaveIO)
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//( if(!isTileLink) { IO(new MacIO with MDIO with MacWishboneMasterIO with MacWishboneSlaveIO) } //else {IO(new MacIO with MDIO with MacWishboneMasterIO)} )
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val m_wb_adr_tmp = Wire(UInt(30.W))
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val wb_dbg_dat0 = Wire(UInt(32.W))
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val r_ClkDiv = Wire(UInt(8.W))
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val r_MiiNoPre = Wire(Bool())
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val r_CtrlData = Wire(UInt(16.W))
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val r_FIAD = Wire(UInt(5.W))
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val r_RGAD = Wire(UInt(5.W))
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val r_WCtrlData = Wire(Bool())
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val r_RStat = Wire(Bool())
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val r_ScanStat = Wire(Bool())
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val NValid_stat = Wire(Bool())
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val Busy_stat = Wire(Bool())
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val LinkFail = Wire(Bool())
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val Prsd = Wire(UInt(16.W))
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val WCtrlDataStart = Wire(Bool())
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val RStatStart = Wire(Bool())
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val UpdateMIIRX_DATAReg = Wire(Bool())
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val TxStartFrm = Wire(Bool())
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val TxEndFrm = Wire(Bool())
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val TxUsedData = Wire(Bool())
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val TxData = Wire(UInt(8.W))
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val TxRetry = Wire(Bool())
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val TxAbort = Wire(Bool())
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val TxUnderRun = Wire(Bool())
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val TxDone = Wire(Bool())
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val RstTxPauseRq = RegInit(Bool())
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val TPauseRq = Wire(Bool())
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// Connecting Miim module
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val miim = Module(new MIIM)
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miim.io.Divider := r_ClkDiv
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miim.io.NoPre := r_MiiNoPre
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miim.io.WCtrlData := r_WCtrlData
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miim.io.CtrlData := r_CtrlData
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miim.io.Fiad := r_FIAD
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miim.io.Rgad := r_RGAD
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miim.io.RStat := r_RStat
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miim.io.ScanStat := r_ScanStat
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miim.io.mdi := io.mdi
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Busy_stat := miim.io.Busy
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LinkFail := miim.io.LinkFail
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NValid_stat := miim.io.Nvalid
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Prsd := miim.io.Prsd
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WCtrlDataStart := miim.io.WCtrlDataStart
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RStatStart := miim.io.RStatStart
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UpdateMIIRX_DATAReg := miim.io.UpdateMIIRX_DATAReg
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io.mdc := miim.io.mdc
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io.mdo := miim.io.mdo
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io.mdoEn := miim.io.mdoEn
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val RegDataOut = Wire(UInt(32.W))
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val r_RecSmall = Wire(Bool())
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val r_LoopBck = Wire(Bool())
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val r_TxEn = Wire(Bool())
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val r_RxEn = Wire(Bool())
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val MRxDV_Lb = Wire(Bool())
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val MRxErr_Lb = Wire(Bool())
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val MRxD_Lb = Wire(UInt(4.W))
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val Transmitting = Wire(Bool())
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val r_HugEn = Wire(Bool())
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val r_DlyCrcEn = Wire(Bool())
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val r_MaxFL = Wire(UInt(16.W))
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val r_MinFL = Wire(UInt(16.W))
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val ShortFrame = Wire(Bool())
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val DribbleNibble = Wire(Bool())
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val ReceivedPacketTooBig = Wire(Bool())
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val r_MAC = Wire(UInt(48.W))
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val LoadRxStatus = Wire(Bool())
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val r_HASH0 = Wire(UInt(32.W))
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val r_HASH1 = Wire(UInt(32.W))
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val r_TxBDNum = Wire(UInt(8.W))
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val r_IPGT = Wire(UInt(7.W))
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val r_IPGR1 = Wire(UInt(7.W))
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val r_IPGR2 = Wire(UInt(7.W))
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val r_CollValid = Wire(UInt(6.W))
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val r_TxPauseTV = Wire(UInt(16.W))
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val r_TxPauseRq = Wire(Bool())
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val r_MaxRet = Wire(UInt(4.W))
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val r_NoBckof = Wire(Bool())
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val r_ExDfrEn = Wire(Bool())
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val r_TxFlow = Wire(Bool())
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val r_IFG = Wire(Bool())
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val TxB_IRQ = Wire(Bool())
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val TxE_IRQ = Wire(Bool())
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val RxB_IRQ = Wire(Bool())
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val RxE_IRQ = Wire(Bool())
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val Busy_IRQ = Wire(Bool())
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val r_Pad = Wire(Bool())
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val r_CrcEn = Wire(Bool())
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val r_FullD = Wire(Bool())
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val r_Pro = Wire(Bool())
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val r_Bro = Wire(Bool())
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val r_NoPre = Wire(Bool())
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val r_RxFlow = Wire(Bool())
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val r_PassAll = Wire(Bool())
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val TxCtrlEndFrm = Wire(Bool())
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val StartTxDone = Wire(Bool())
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val SetPauseTimer = Wire(Bool())
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val TxUsedDataIn = Wire(Bool())
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val TxDoneIn = Wire(Bool())
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val TxAbortIn = Wire(Bool())
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val PerPacketPad = Wire(Bool())
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val PadOut = Wire(Bool())
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val PerPacketCrcEn = Wire(Bool())
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val CrcEnOut = Wire(Bool())
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val TxStartFrmOut = Wire(Bool())
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val TxEndFrmOut = Wire(Bool())
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val ReceivedPauseFrm = Wire(Bool())
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val ControlFrmAddressOK = Wire(Bool())
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val RxStatusWriteLatched_sync2 = Wire(Bool())
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val LateCollision = Wire(Bool())
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val DeferIndication = Wire(Bool())
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val LateCollLatched = Wire(Bool())
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val DeferLatched = Wire(Bool())
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val RstDeferLatched = Wire(Bool())
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val CarrierSenseLost = Wire(Bool())
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val RegCs = Wire(UInt(4.W))
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val ethReg = Module(new MacReg)
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ethReg.io.DataIn := io.WB_DAT_I
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ethReg.io.Address := io.WB_ADR_I(9,2)
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ethReg.io.Rw := io.WB_WE_I
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ethReg.io.Cs := RegCs
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ethReg.io.WCtrlDataStart := WCtrlDataStart
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ethReg.io.RStatStart := RStatStart
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ethReg.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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ethReg.io.Prsd := Prsd
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ethReg.io.NValid_stat := NValid_stat
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ethReg.io.Busy_stat := Busy_stat
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ethReg.io.LinkFail := LinkFail
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ethReg.io.TxB_IRQ := TxB_IRQ
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ethReg.io.TxE_IRQ := TxE_IRQ
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ethReg.io.RxB_IRQ := RxB_IRQ
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ethReg.io.RxE_IRQ := RxE_IRQ
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ethReg.io.Busy_IRQ := Busy_IRQ
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ethReg.io.RstTxPauseRq := RstTxPauseRq
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ethReg.io.TxCtrlEndFrm := TxCtrlEndFrm
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ethReg.io.StartTxDone := StartTxDone
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ethReg.io.TxClk := io.mtx_clk_pad_i
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ethReg.io.RxClk := io.mrx_clk_pad_i
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ethReg.io.SetPauseTimer := SetPauseTimer
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ethReg.io.dbg_dat := wb_dbg_dat0
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RegDataOut := ethReg.io.DataOut
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r_RecSmall := ethReg.io.r_RecSmall
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r_Pad := ethReg.io.r_Pad
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r_HugEn := ethReg.io.r_HugEn
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r_CrcEn := ethReg.io.r_CrcEn
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r_DlyCrcEn := ethReg.io.r_DlyCrcEn
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r_FullD := ethReg.io.r_FullD
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r_ExDfrEn := ethReg.io.r_ExDfrEn
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r_NoBckof := ethReg.io.r_NoBckof
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r_LoopBck := ethReg.io.r_LoopBck
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r_IFG := ethReg.io.r_IFG
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r_Pro := ethReg.io.r_Pro
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r_Bro := ethReg.io.r_Bro
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r_NoPre := ethReg.io.r_NoPre
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r_TxEn := ethReg.io.r_TxEn
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r_RxEn := ethReg.io.r_RxEn
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r_HASH0 := ethReg.io.r_HASH0
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r_HASH1 := ethReg.io.r_HASH1
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r_IPGT := ethReg.io.r_IPGT
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r_IPGR1 := ethReg.io.r_IPGR1
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r_IPGR2 := ethReg.io.r_IPGR2
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r_MinFL := ethReg.io.r_MinFL
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r_MaxFL := ethReg.io.r_MaxFL
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r_MaxRet := ethReg.io.r_MaxRet
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r_CollValid := ethReg.io.r_CollValid
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r_TxFlow := ethReg.io.r_TxFlow
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r_RxFlow := ethReg.io.r_RxFlow
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r_PassAll := ethReg.io.r_PassAll
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r_MiiNoPre := ethReg.io.r_MiiNoPre
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r_ClkDiv := ethReg.io.r_ClkDiv
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r_WCtrlData := ethReg.io.r_WCtrlData
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r_RStat := ethReg.io.r_RStat
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r_ScanStat := ethReg.io.r_ScanStat
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r_RGAD := ethReg.io.r_RGAD
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r_FIAD := ethReg.io.r_FIAD
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r_CtrlData := ethReg.io.r_CtrlData
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r_MAC := ethReg.io.r_MAC
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r_TxBDNum := ethReg.io.r_TxBDNum
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io.int_o := ethReg.io.int_o
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r_TxPauseTV := ethReg.io.r_TxPauseTV
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r_TxPauseRq := ethReg.io.r_TxPauseRq
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val RxData = Wire(UInt(8.W))
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val RxValid = Wire(Bool())
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val RxStartFrm = Wire(Bool())
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val RxEndFrm = Wire(Bool())
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val RxAbort = Wire(Bool())
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val WillTransmit = Wire(Bool())
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val ResetCollision = Wire(Bool())
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val TxDataOut = Wire(UInt(8.W))
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val WillSendControlFrame = Wire(Bool())
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val ReceiveEnd = Wire(Bool())
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val ReceivedPacketGood = Wire(Bool())
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val ReceivedLengthOK = Wire(Bool())
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val InvalidSymbol = Wire(Bool())
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val LatchedCrcError = Wire(Bool())
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val RxLateCollision = Wire(Bool())
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val RetryCntLatched = Wire(UInt(4.W))
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val RetryCnt = Wire(UInt(4.W))
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val StartTxAbort = Wire(Bool())
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val MaxCollisionOccured = Wire(Bool())
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val RetryLimit = Wire(Bool())
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val StatePreamble = Wire(Bool())
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val StateData = Wire(UInt(2.W))
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// Connecting MACControl
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val maccontrol = Module(new MacControl)
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maccontrol.io.MTxClk := io.mtx_clk_pad_i
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maccontrol.io.MRxClk := io.mrx_clk_pad_i
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maccontrol.io.TxReset := reset.asBool
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maccontrol.io.RxReset := reset.asBool
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maccontrol.io.TPauseRq := TPauseRq
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maccontrol.io.TxDataIn := TxData
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maccontrol.io.TxStartFrmIn := TxStartFrm
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maccontrol.io.TxUsedDataIn := TxUsedDataIn
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maccontrol.io.TxEndFrmIn := TxEndFrm
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maccontrol.io.TxDoneIn := TxDoneIn
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maccontrol.io.TxAbortIn := TxAbortIn
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maccontrol.io.PadIn := r_Pad | PerPacketPad
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maccontrol.io.CrcEnIn := r_CrcEn | PerPacketCrcEn
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maccontrol.io.RxData := RxData
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maccontrol.io.RxValid := RxValid
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maccontrol.io.RxStartFrm := RxStartFrm
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maccontrol.io.RxEndFrm := RxEndFrm
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maccontrol.io.ReceiveEnd := ReceiveEnd
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maccontrol.io.ReceivedPacketGood := ReceivedPacketGood
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maccontrol.io.ReceivedLengthOK := ReceivedLengthOK
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maccontrol.io.TxFlow := r_TxFlow
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maccontrol.io.RxFlow := r_RxFlow
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maccontrol.io.DlyCrcEn := r_DlyCrcEn
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maccontrol.io.TxPauseTV := r_TxPauseTV
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maccontrol.io.MAC := r_MAC
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maccontrol.io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync2
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maccontrol.io.r_PassAll := r_PassAll
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TxDataOut := maccontrol.io.TxDataOut
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TxStartFrmOut := maccontrol.io.TxStartFrmOut
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TxEndFrmOut := maccontrol.io.TxEndFrmOut
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TxDone := maccontrol.io.TxDoneOut
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TxAbort := maccontrol.io.TxAbortOut
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TxUsedData := maccontrol.io.TxUsedDataOut
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PadOut := maccontrol.io.PadOut
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CrcEnOut := maccontrol.io.CrcEnOut
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WillSendControlFrame := maccontrol.io.WillSendControlFrame
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TxCtrlEndFrm := maccontrol.io.TxCtrlEndFrm
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ReceivedPauseFrm := maccontrol.io.ReceivedPauseFrm
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ControlFrmAddressOK := maccontrol.io.ControlFrmAddressOK
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SetPauseTimer := maccontrol.io.SetPauseTimer
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val TxCarrierSense = Wire(Bool())
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val Collision = Wire(Bool())
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val CarrierSense_Tx2 = Wire(Bool())
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val RxEnSync = Wire(Bool())
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// Muxed MII receive data valid
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MRxDV_Lb := Mux(r_LoopBck, io.mtxen_pad_o, io.mrxdv_pad_i & RxEnSync)
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// Muxed MII Receive Error
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MRxErr_Lb := Mux(r_LoopBck, io.mtxerr_pad_o, io.mrxerr_pad_i & RxEnSync)
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// Muxed MII Receive Data
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MRxD_Lb := Mux(r_LoopBck, io.mtxd_pad_o, io.mrxd_pad_i)
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val txethmac = Module(new MacTx)
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txethmac.clock := io.mtx_clk_pad_i
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txethmac.reset := reset.asBool
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txethmac.io.TxStartFrm := TxStartFrmOut
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txethmac.io.TxEndFrm := TxEndFrmOut
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txethmac.io.TxUnderRun := TxUnderRun
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txethmac.io.TxData := TxDataOut
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txethmac.io.CarrierSense := TxCarrierSense
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txethmac.io.Collision := Collision
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txethmac.io.Pad := PadOut
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txethmac.io.CrcEn := CrcEnOut
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txethmac.io.FullD := r_FullD
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txethmac.io.HugEn := r_HugEn
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txethmac.io.DlyCrcEn := r_DlyCrcEn
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txethmac.io.MinFL := r_MinFL
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txethmac.io.MaxFL := r_MaxFL
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txethmac.io.IPGT := r_IPGT
|
||||
txethmac.io.IPGR1 := r_IPGR1
|
||||
txethmac.io.IPGR2 := r_IPGR2
|
||||
txethmac.io.CollValid := r_CollValid
|
||||
txethmac.io.MaxRet := r_MaxRet
|
||||
txethmac.io.NoBckof := r_NoBckof
|
||||
txethmac.io.ExDfrEn := r_ExDfrEn
|
||||
|
||||
io.mtxd_pad_o := txethmac.io.MTxD
|
||||
io.mtxen_pad_o := txethmac.io.MTxEn
|
||||
io. mtxerr_pad_o := txethmac.io.MTxErr
|
||||
TxDoneIn := txethmac.io.TxDone
|
||||
TxRetry := txethmac.io.TxRetry
|
||||
TxAbortIn := txethmac.io.TxAbort
|
||||
TxUsedDataIn := txethmac.io.TxUsedData
|
||||
WillTransmit := txethmac.io.WillTransmit
|
||||
ResetCollision := txethmac.io.ResetCollision
|
||||
RetryCnt := txethmac.io.RetryCnt
|
||||
StartTxDone := txethmac.io.StartTxDone
|
||||
StartTxAbort := txethmac.io.StartTxAbort
|
||||
MaxCollisionOccured := txethmac.io.MaxCollisionOccured
|
||||
LateCollision := txethmac.io.LateCollision
|
||||
DeferIndication := txethmac.io.DeferIndication
|
||||
StatePreamble := txethmac.io.StatePreamble
|
||||
StateData := txethmac.io.StateData
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val RxByteCnt = Wire(UInt(16.W))
|
||||
val RxByteCntEq0 = Wire(Bool())
|
||||
val RxByteCntGreat2 = Wire(Bool())
|
||||
val RxByteCntMaxFrame = Wire(Bool())
|
||||
val RxCrcError = Wire(Bool())
|
||||
val RxStateIdle = Wire(Bool())
|
||||
val RxStatePreamble = Wire(Bool())
|
||||
val RxStateSFD = Wire(Bool())
|
||||
val RxStateData = Wire(UInt(2.W))
|
||||
val AddressMiss = Wire(Bool())
|
||||
|
||||
|
||||
val rxethmac = Module(new MacRx)
|
||||
rxethmac.clock := io.mrx_clk_pad_i
|
||||
rxethmac.reset := reset.asBool
|
||||
rxethmac.io.MRxDV := MRxDV_Lb
|
||||
rxethmac.io.MRxD := MRxD_Lb
|
||||
rxethmac.io.Transmitting := Transmitting
|
||||
rxethmac.io.HugEn := r_HugEn
|
||||
rxethmac.io.DlyCrcEn := r_DlyCrcEn
|
||||
rxethmac.io.MaxFL := r_MaxFL
|
||||
rxethmac.io.r_IFG := r_IFG
|
||||
rxethmac.io.MAC := r_MAC
|
||||
rxethmac.io.r_Bro := r_Bro
|
||||
rxethmac.io.r_Pro := r_Pro
|
||||
rxethmac.io.r_HASH0 := r_HASH0
|
||||
rxethmac.io.r_HASH1 := r_HASH1
|
||||
rxethmac.io.PassAll := r_PassAll
|
||||
rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK
|
||||
|
||||
RxData := rxethmac.io.RxData
|
||||
RxValid := rxethmac.io.RxValid
|
||||
RxStartFrm := rxethmac.io.RxStartFrm
|
||||
RxEndFrm := rxethmac.io.RxEndFrm
|
||||
RxByteCnt := rxethmac.io.ByteCnt
|
||||
RxByteCntEq0 := rxethmac.io.ByteCntEq0
|
||||
RxByteCntGreat2 := rxethmac.io.ByteCntGreat2
|
||||
RxByteCntMaxFrame := rxethmac.io.ByteCntMaxFrame
|
||||
RxCrcError := rxethmac.io.CrcError
|
||||
RxStateIdle := rxethmac.io.StateIdle
|
||||
RxStatePreamble := rxethmac.io.StatePreamble
|
||||
RxStateSFD := rxethmac.io.StateSFD
|
||||
RxStateData := rxethmac.io.StateData
|
||||
RxAbort := rxethmac.io.RxAbort
|
||||
AddressMiss := rxethmac.io.AddressMiss
|
||||
|
||||
|
||||
withClockAndReset( io.mtx_clk_pad_i.asClock, reset ) {
|
||||
// MII Carrier Sense Synchronization
|
||||
CarrierSense_Tx2 := ShiftRegister(io.mcrs_pad_i, 2, false.B, true.B)
|
||||
|
||||
TxCarrierSense := ~r_FullD & CarrierSense_Tx2
|
||||
|
||||
val Collision_Tx1 = RegNext(io.mcoll_pad_i, false.B)
|
||||
val Collision_Tx2 = RegInit(false.B)
|
||||
|
||||
when(ResetCollision){
|
||||
Collision_Tx2 := false.B
|
||||
} .elsewhen(Collision_Tx1){
|
||||
Collision_Tx2 := true.B
|
||||
}
|
||||
|
||||
|
||||
// Synchronized Collision
|
||||
Collision := ~r_FullD & Collision_Tx2
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
withClockAndReset( io.mrx_clk_pad_i.asClock, reset ) {
|
||||
val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)
|
||||
|
||||
Transmitting := ~r_FullD & WillTransmit_q
|
||||
RxEnSync := RegEnable(r_RxEn, false.B, ~io.mrxdv_pad_i)
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// Synchronizing WillSendControlFrame to WB_CLK;
|
||||
val WillSendControlFrame_sync = ShiftRegisters(WillSendControlFrame, 3, false.B, true.B)
|
||||
|
||||
when(true.B){
|
||||
RstTxPauseRq := WillSendControlFrame_sync(1) & ~WillSendControlFrame_sync(2)
|
||||
}
|
||||
|
||||
|
||||
withClockAndReset( io.mtx_clk_pad_i.asClock, reset ) {
|
||||
val TxPauseRq_sync = ShiftRegisters((r_TxPauseRq & r_TxFlow), 3, false.B, true.B )
|
||||
|
||||
TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
|
||||
}
|
||||
|
||||
val LatchedMRxErr = Wire(Bool())
|
||||
|
||||
|
||||
|
||||
|
||||
val RxAbort_latch_wire = Wire(Bool())
|
||||
val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
|
||||
|
||||
withClockAndReset( io.mrx_clk_pad_i.asClock, reset ) {
|
||||
val RxAbort_latch = RegInit(false.B)
|
||||
val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
|
||||
|
||||
// Synchronizing RxAbort to the WISHBONE clock
|
||||
when(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))){
|
||||
RxAbort_latch := true.B
|
||||
} .elsewhen(RxAbortRst){
|
||||
RxAbort_latch := false.B
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
val wishbone = Module(new MacTileLink)
|
||||
|
||||
wishbone.io.WB_DAT_I := io.WB_DAT_I
|
||||
io.WB_DAT_O := wishbone.io.WB_DAT_O
|
||||
wishbone.io.WB_ADR_I := io.WB_ADR_I
|
||||
wishbone.io.WB_WE_I := io.WB_WE_I
|
||||
wishbone.io.WB_SEL_I := io.WB_SEL_I
|
||||
wishbone.io.WB_CYC_I := io.WB_CYC_I
|
||||
wishbone.io.WB_STB_I := io.WB_STB_I
|
||||
io.WB_ACK_O := wishbone.io.WB_ACK_O
|
||||
io.WB_ERR_O := wishbone.io.WB_ERR_O
|
||||
|
||||
|
||||
m_wb_adr_tmp := wishbone.io.m_wb_adr_o
|
||||
io.m_wb_sel_o := wishbone.io.m_wb_sel_o
|
||||
io.m_wb_we_o := wishbone.io.m_wb_we_o
|
||||
io.m_wb_dat_o := wishbone.io.m_wb_dat_o
|
||||
io.m_wb_cyc_o := wishbone.io.m_wb_cyc_o
|
||||
io.m_wb_stb_o := wishbone.io.m_wb_stb_o
|
||||
wishbone.io.m_wb_dat_i := io.m_wb_dat_i
|
||||
wishbone.io.m_wb_ack_i := io.m_wb_ack_i
|
||||
wishbone.io.m_wb_err_i := io.m_wb_err_i
|
||||
io.m_wb_cti_o := wishbone.io.m_wb_cti_o
|
||||
io.m_wb_bte_o := wishbone.io.m_wb_bte_o
|
||||
|
||||
wishbone.io.InvalidSymbol := InvalidSymbol
|
||||
wishbone.io.LatchedCrcError := LatchedCrcError
|
||||
wishbone.io.RxLateCollision := RxLateCollision
|
||||
wishbone.io.ShortFrame := ShortFrame
|
||||
wishbone.io.DribbleNibble := DribbleNibble
|
||||
wishbone.io.ReceivedPacketTooBig := ReceivedPacketTooBig
|
||||
wishbone.io.RxLength := RxByteCnt
|
||||
wishbone.io.LoadRxStatus := LoadRxStatus
|
||||
wishbone.io.ReceivedPacketGood := ReceivedPacketGood
|
||||
wishbone.io.AddressMiss := AddressMiss
|
||||
wishbone.io.r_RxFlow := r_RxFlow
|
||||
wishbone.io.r_PassAll := r_PassAll
|
||||
wishbone.io.ReceivedPauseFrm := ReceivedPauseFrm
|
||||
|
||||
wishbone.io.RetryCntLatched := RetryCntLatched
|
||||
wishbone.io.RetryLimit := RetryLimit
|
||||
wishbone.io.LateCollLatched := LateCollLatched
|
||||
wishbone.io.DeferLatched := DeferLatched
|
||||
RstDeferLatched := wishbone.io.RstDeferLatched
|
||||
wishbone.io.CarrierSenseLost := CarrierSenseLost
|
||||
|
||||
wishbone.io.MTxClk := io.mtx_clk_pad_i
|
||||
wishbone.io.TxUsedData := TxUsedData
|
||||
wishbone.io.TxRetry := TxRetry
|
||||
wishbone.io.TxAbort := TxAbort
|
||||
wishbone.io.TxDone := TxDone
|
||||
TxStartFrm := wishbone.io.TxStartFrm
|
||||
TxEndFrm := wishbone.io.TxEndFrm
|
||||
TxData := wishbone.io.TxData
|
||||
TxUnderRun := wishbone.io.TxUnderRun
|
||||
PerPacketCrcEn := wishbone.io.PerPacketCrcEn
|
||||
PerPacketPad := wishbone.io.PerPacketPad
|
||||
|
||||
wishbone.io.MRxClk := io.mrx_clk_pad_i
|
||||
wishbone.io.RxData := RxData
|
||||
wishbone.io.RxValid := RxValid
|
||||
wishbone.io.RxStartFrm := RxStartFrm
|
||||
wishbone.io.RxEndFrm := RxEndFrm
|
||||
wishbone.io.RxAbort := RxAbort_wb
|
||||
RxStatusWriteLatched_sync2 := wishbone.io.RxStatusWriteLatched_sync2
|
||||
|
||||
wishbone.io.r_TxEn := r_TxEn
|
||||
wishbone.io.r_RxEn := r_RxEn
|
||||
wishbone.io.r_TxBDNum := r_TxBDNum
|
||||
wishbone.io.RegDataOut := RegDataOut
|
||||
RegCs := wishbone.io.RegCs
|
||||
TxB_IRQ := wishbone.io.TxB_IRQ
|
||||
TxE_IRQ := wishbone.io.TxE_IRQ
|
||||
RxB_IRQ := wishbone.io.RxB_IRQ
|
||||
RxE_IRQ := wishbone.io.RxE_IRQ
|
||||
Busy_IRQ := wishbone.io.Busy_IRQ
|
||||
|
||||
|
||||
|
||||
io.m_wb_adr_o := Cat(m_wb_adr_tmp, 0.U(2.W))
|
||||
|
||||
val macstatus = Module(new MacStatus)
|
||||
|
||||
macstatus.io.reset := reset.asBool
|
||||
macstatus.io.MRxClk := io.mrx_clk_pad_i
|
||||
macstatus.io.RxCrcError := RxCrcError
|
||||
macstatus.io.MRxErr := MRxErr_Lb
|
||||
macstatus.io.MRxDV := MRxDV_Lb
|
||||
macstatus.io.RxStateSFD := RxStateSFD
|
||||
macstatus.io.RxStateData := RxStateData
|
||||
macstatus.io.RxStatePreamble := RxStatePreamble
|
||||
macstatus.io.RxStateIdle := RxStateIdle
|
||||
macstatus.io.Transmitting := Transmitting
|
||||
macstatus.io.RxByteCnt := RxByteCnt
|
||||
macstatus.io.RxByteCntEq0 := RxByteCntEq0
|
||||
macstatus.io.RxByteCntGreat2 := RxByteCntGreat2
|
||||
macstatus.io.RxByteCntMaxFrame := RxByteCntMaxFrame
|
||||
macstatus.io.MRxD := MRxD_Lb
|
||||
macstatus.io.Collision := io.mcoll_pad_i
|
||||
macstatus.io.CollValid := r_CollValid
|
||||
macstatus.io.r_RecSmall := r_RecSmall
|
||||
macstatus.io.r_MinFL := r_MinFL
|
||||
macstatus.io.r_MaxFL := r_MaxFL
|
||||
macstatus.io.r_HugEn := r_HugEn
|
||||
macstatus.io.StartTxDone := StartTxDone
|
||||
macstatus.io.StartTxAbort := StartTxAbort
|
||||
macstatus.io.RetryCnt := RetryCnt
|
||||
macstatus.io.MTxClk := io.mtx_clk_pad_i
|
||||
macstatus.io.MaxCollisionOccured := MaxCollisionOccured
|
||||
macstatus.io.LateCollision := LateCollision
|
||||
macstatus.io.DeferIndication := DeferIndication
|
||||
macstatus.io.TxStartFrm := TxStartFrmOut
|
||||
macstatus.io.StatePreamble := StatePreamble
|
||||
macstatus.io.StateData := StateData
|
||||
macstatus.io.CarrierSense := CarrierSense_Tx2
|
||||
macstatus.io.TxUsedData := TxUsedDataIn
|
||||
macstatus.io.Loopback := r_LoopBck
|
||||
macstatus.io.r_FullD := r_FullD
|
||||
macstatus.io.RstDeferLatched := RstDeferLatched
|
||||
|
||||
ReceivedLengthOK := macstatus.io.ReceivedLengthOK
|
||||
ReceiveEnd := macstatus.io.ReceiveEnd
|
||||
ReceivedPacketGood := macstatus.io.ReceivedPacketGood
|
||||
InvalidSymbol := macstatus.io.InvalidSymbol
|
||||
LatchedCrcError := macstatus.io.LatchedCrcError
|
||||
RxLateCollision := macstatus.io.RxLateCollision
|
||||
ShortFrame := macstatus.io.ShortFrame
|
||||
DribbleNibble := macstatus.io.DribbleNibble
|
||||
ReceivedPacketTooBig := macstatus.io.ReceivedPacketTooBig
|
||||
LoadRxStatus := macstatus.io.LoadRxStatus
|
||||
RetryCntLatched := macstatus.io.RetryCntLatched
|
||||
RetryLimit := macstatus.io.RetryLimit
|
||||
LateCollLatched := macstatus.io.LateCollLatched
|
||||
DeferLatched := macstatus.io.DeferLatched
|
||||
CarrierSenseLost := macstatus.io.CarrierSenseLost
|
||||
LatchedMRxErr := macstatus.io.LatchedMRxErr
|
||||
|
||||
}
|
||||
|
||||
@@ -3,14 +3,14 @@ package MAC
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
class MDIO extends Bundle{
|
||||
trait MDIO { this: Bundle =>
|
||||
val mdi = Input( Bool()) // MII Management Data In
|
||||
val mdc = Output(Bool()) // MII Management Data Clock
|
||||
val mdo = Output(Bool()) // MII Management Data Output
|
||||
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
||||
}
|
||||
|
||||
class MIIMIO extends MDIO{
|
||||
class MIIMIO extends Bundle with MDIO{
|
||||
val Divider = Input( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
||||
val NoPre = Input(Bool()) // No Preamble (no 32-bit preamble)
|
||||
|
||||
|
||||
@@ -4,6 +4,9 @@ import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
class MacStatusIO extends Bundle{
|
||||
val reset = Input(Bool())
|
||||
|
||||
val MRxClk = Input(Bool())
|
||||
val RxCrcError = Input(Bool())
|
||||
val MRxErr = Input(Bool())
|
||||
val MRxDV = Input(Bool())
|
||||
@@ -57,9 +60,10 @@ class MacStatusIO extends Bundle{
|
||||
val LatchedMRxErr = Output(Bool())
|
||||
}
|
||||
|
||||
class MacStatus extends Module{
|
||||
class MacStatus extends RawModule{
|
||||
val io: MacStatusIO = IO(new MacStatusIO)
|
||||
|
||||
withClockAndReset( io.MRxClk.asClock, io.reset ) {
|
||||
|
||||
val LatchedCrcError = RegInit(false.B); io.LatchedCrcError := LatchedCrcError // Crc error
|
||||
|
||||
@@ -140,6 +144,12 @@ class MacStatus extends Module{
|
||||
ReceivedPacketTooBig := ~io.r_HugEn & io.RxByteCnt > io.r_MaxFL
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
withClockAndReset( io.MTxClk.asClock, io.reset ) {
|
||||
val RetryCntLatched = RegEnable( io.RetryCnt, 0.U(4.W), io.StartTxDone | io.StartTxAbort); io.RetryCntLatched := RetryCntLatched
|
||||
val RetryLimit = RegEnable( io.MaxCollisionOccured, false.B, io.StartTxDone | io.StartTxAbort ); io.RetryLimit := RetryLimit // Latched Retransmission limit
|
||||
val LateCollLatched = RegEnable( io.LateCollision, false.B, io.StartTxDone | io.StartTxAbort); io.LateCollLatched := LateCollLatched // Latched Late Collision
|
||||
@@ -153,7 +163,6 @@ class MacStatus extends Module{
|
||||
DeferLatched := false.B
|
||||
}
|
||||
|
||||
|
||||
val CarrierSenseLost = RegInit(false.B); io.CarrierSenseLost := CarrierSenseLost // CarrierSenseLost
|
||||
|
||||
when((io.StatePreamble | io.StateData.orR) & ~io.CarrierSense & ~io.Loopback & ~io.Collision & ~io.r_FullD){
|
||||
@@ -162,6 +171,10 @@ class MacStatus extends Module{
|
||||
CarrierSenseLost := false.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -44,28 +44,14 @@ class RxBuffDesc extends Bundle{
|
||||
|
||||
|
||||
|
||||
abstract class MacTileLinkBase(edge: TLEdgeIn) extends Module{
|
||||
trait MacTileLinkSlaveIO { this: Bundle =>
|
||||
val slvA = Flipped(Decoupled(new TLBundleA(edge.bundle)))
|
||||
val slvD = Decoupled(new TLBundleD(edge.bundle))
|
||||
}
|
||||
abstract class MacTileLinkBase() extends Module{
|
||||
// edge: TLEdgeIn
|
||||
// trait MacTileLinkSlaveIO { this: Bundle =>
|
||||
// val slvA = Flipped(Decoupled(new TLBundleA(edge.bundle)))
|
||||
// val slvD = Decoupled(new TLBundleD(edge.bundle))
|
||||
// }
|
||||
|
||||
trait MacWishboneSlaveIO{ this: Bundle =>
|
||||
// WISHBONE common
|
||||
val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input
|
||||
val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output
|
||||
|
||||
// WISHBONE slave
|
||||
val WB_ADR_I = Input(UInt(10.W)) // WISHBONE address input
|
||||
val WB_WE_I = Input(Bool()) // WISHBONE write enable input
|
||||
// val BDCs = Input(UInt(4.W)) // Buffer descriptors are selected
|
||||
val WB_SEL_I = Input(UInt(4.W)) // WISHBONE byte select input
|
||||
val WB_CYC_I = Input(Bool()) // WISHBONE cycle input
|
||||
val WB_STB_I = Input(Bool()) // WISHBONE strobe input
|
||||
|
||||
val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output
|
||||
val WB_ERR_O = Output(Bool()) // WISHBONE error output
|
||||
}
|
||||
|
||||
class MacTileLinkIO extends Bundle{
|
||||
|
||||
@@ -144,9 +130,10 @@ abstract class MacTileLinkBase(edge: TLEdgeIn) extends Module{
|
||||
}
|
||||
|
||||
|
||||
def isTileLink = false.B
|
||||
def isTileLink = false
|
||||
|
||||
val io: MacTileLinkIO = if( !isTileLink ) {IO(new MacTileLinkIO with MacWishboneSlaveIO)} else {IO(new MacTileLinkIO with MacTileLinkSlaveIO)}
|
||||
val io = IO(new MacTileLinkIO with MacWishboneSlaveIO)
|
||||
// if( !isTileLink ) {IO(new MacTileLinkIO with MacWishboneSlaveIO)} else {IO(new MacTileLinkIO with MacTileLinkSlaveIO)}
|
||||
|
||||
|
||||
|
||||
@@ -421,10 +408,16 @@ abstract class MacTileLinkBase(edge: TLEdgeIn) extends Module{
|
||||
WbEn := true.B // RxEn access stage and r_TxEn is disabled
|
||||
RxEn := false.B
|
||||
TxEn := false.B
|
||||
ram_addr := (if( !isTileLink ) {io.WB_ADR_I(7,0)} else {io.slvA.bits.address(9:2)}) // [11:2 ] -> [9:2];
|
||||
ram_di := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
BDWrite := (if( !isTileLink ) {BDCs & Fill(4,io.WB_WE_I)} else {BDCs & Fill(4,(io.slvA.bits.opcode === 0.U) || (io.slvA.bits.opcode === 1.U))} )
|
||||
BDRead := (if( !isTileLink ) {BDCs.orR & ~io.WB_WE_I} else {BDCs.orR & (io.slvA.bits.opcode === 4.U)})
|
||||
|
||||
ram_addr := io.WB_ADR_I(9,2)
|
||||
ram_di := io.WB_DAT_I
|
||||
BDWrite := BDCs & Fill(4,io.WB_WE_I)
|
||||
BDRead := BDCs.orR & ~io.WB_WE_I
|
||||
|
||||
// ram_addr := (if( !isTileLink ) {io.WB_ADR_I(9,2)} else {io.slvA.bits.address(9,2)}) // [11:2 ] -> [9:2];
|
||||
// ram_di := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
// BDWrite := (if( !isTileLink ) {BDCs & Fill(4,io.WB_WE_I)} else {BDCs & Fill(4,(io.slvA.bits.opcode === 0.U) || (io.slvA.bits.opcode === 1.U))} )
|
||||
// BDRead := (if( !isTileLink ) {BDCs.orR & ~io.WB_WE_I} else {BDCs.orR & (io.slvA.bits.opcode === 4.U)})
|
||||
} .elsewhen( RAMAccessEnable === BitPat("b010?1") ){
|
||||
WbEn := false.B
|
||||
RxEn := false.B
|
||||
@@ -435,20 +428,30 @@ abstract class MacTileLinkBase(edge: TLEdgeIn) extends Module{
|
||||
WbEn := true.B // TxEn access stage (we always go to wb access stage)
|
||||
RxEn := false.B
|
||||
TxEn := false.B
|
||||
ram_addr := (if( !isTileLink ) {io.WB_ADR_I(7,0)} else {io.slvA.bits.address(9:2)}) //[11:2 ] ->[9:2]
|
||||
ram_di := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
BDWrite := (if( !isTileLink ) {BDCs & Fill(4,io.WB_WE_I)} else {BDCs & Fill(4,(io.slvA.bits.opcode === 0.U) || (io.slvA.bits.opcode === 1.U))} )
|
||||
BDRead := (if( !isTileLink ) {BDCs.orR & ~io.WB_WE_I} else {BDCs.orR & (io.slvA.bits.opcode === 4.U)})
|
||||
ram_addr := io.WB_ADR_I(9,2)
|
||||
ram_di := io.WB_DAT_I
|
||||
BDWrite := BDCs & Fill(4,io.WB_WE_I)
|
||||
BDRead := BDCs.orR & ~io.WB_WE_I
|
||||
|
||||
// ram_addr := (if( !isTileLink ) {io.WB_ADR_I(9,2)} else {io.slvA.bits.address(9,2)}) //[11:2 ] ->[9:2]
|
||||
// ram_di := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
// BDWrite := (if( !isTileLink ) {BDCs & Fill(4,io.WB_WE_I)} else {BDCs & Fill(4,(io.slvA.bits.opcode === 0.U) || (io.slvA.bits.opcode === 1.U))} )
|
||||
// BDRead := (if( !isTileLink ) {BDCs.orR & ~io.WB_WE_I} else {BDCs.orR & (io.slvA.bits.opcode === 4.U)})
|
||||
} .elsewhen( RAMAccessEnable === BitPat("b10000") ){
|
||||
WbEn := false.B // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
|
||||
} .elsewhen( RAMAccessEnable === BitPat("b00000") ){
|
||||
WbEn := true.B // Idle state. We go to WbEn access stage.
|
||||
RxEn := false.B
|
||||
TxEn := false.B
|
||||
ram_addr := (if( !isTileLink ) {io.WB_ADR_I(7,0)} else {io.slvA.bits.address(9:2)}) // [11:2 ] -> [9:2]
|
||||
ram_di := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
BDWrite := (if( !isTileLink ) {BDCs & Fill(4,io.WB_WE_I)} else {BDCs & Fill(4,(io.slvA.bits.opcode === 0.U) || (io.slvA.bits.opcode === 1.U))} )
|
||||
BDRead := (if( !isTileLink ) {BDCs.orR & ~io.WB_WE_I} else {BDCs.orR & (io.slvA.bits.opcode === 4.U)})
|
||||
ram_addr := io.WB_ADR_I(9,2)
|
||||
ram_di := io.WB_DAT_I
|
||||
BDWrite := BDCs & Fill(4,io.WB_WE_I)
|
||||
BDRead := BDCs.orR & ~io.WB_WE_I
|
||||
|
||||
// ram_addr := (if( !isTileLink ) {io.WB_ADR_I(9,2)} else {io.slvA.bits.address(9,2)}) // [11:2 ] -> [9:2]
|
||||
// ram_di := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
// BDWrite := (if( !isTileLink ) {BDCs & Fill(4,io.WB_WE_I)} else {BDCs & Fill(4,(io.slvA.bits.opcode === 0.U) || (io.slvA.bits.opcode === 1.U))} )
|
||||
// BDRead := (if( !isTileLink ) {BDCs.orR & ~io.WB_WE_I} else {BDCs.orR & (io.slvA.bits.opcode === 4.U)})
|
||||
}
|
||||
|
||||
|
||||
@@ -750,7 +753,8 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
|
||||
TxFifoClear := (TxAbortPacket | TxRetryPacket)
|
||||
|
||||
val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
|
||||
tx_fifo.io.data_in := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
tx_fifo.io.data_in := io.WB_DAT_I
|
||||
// tx_fifo.io.data_in := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
|
||||
tx_fifo.io.write := MasterWbTX & io.m_wb_ack_i
|
||||
tx_fifo.io.read := ReadTxDataFromFifo_wb & ~TxBufferEmpty
|
||||
tx_fifo.io.clear := TxFifoClear
|
||||
@@ -1165,32 +1169,32 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
|
||||
val CsMiss = Wire(Bool())
|
||||
|
||||
|
||||
if( !isTileLink ){
|
||||
io.RegCs := Fill(4, io.WB_STB_I & io.WB_CYC_I & io.WB_SEL_I.orR & ~io.WB_ADR_I.extract(9) & ~io.WB_ADR_I.extract(8)) & io.WB_SEL_I // 0x0 - 0x3FF
|
||||
BDCs := Fill(4, io.WB_STB_I & io.WB_CYC_I & io.WB_SEL_I.orR & ~io.WB_ADR_I.extract(9) & io.WB_ADR_I.extract(8)) & io.WB_SEL_I // 0x400 - 0x7FF
|
||||
CsMiss := io.WB_STB_I & io.WB_CYC_I & io.WB_SEL_I.orR & io.WB_ADR_I.extract(9) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
|
||||
// if( !isTileLink ){
|
||||
io.RegCs := Fill(4, io.WB_STB_I & io.WB_CYC_I & io.WB_SEL_I.orR & ~io.WB_ADR_I.extract(11) & ~io.WB_ADR_I.extract(10)) & io.WB_SEL_I // 0x0 - 0x3FF
|
||||
BDCs := Fill(4, io.WB_STB_I & io.WB_CYC_I & io.WB_SEL_I.orR & ~io.WB_ADR_I.extract(11) & io.WB_ADR_I.extract(10)) & io.WB_SEL_I // 0x400 - 0x7FF
|
||||
CsMiss := io.WB_STB_I & io.WB_CYC_I & io.WB_SEL_I.orR & io.WB_ADR_I.extract(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
|
||||
|
||||
io.WB_DAT_O := RegNext(Mux( ((io.RegCs.orR) & ~io.WB_WE_I), io.RegDataOut, BD_WB_DAT_O ), 0.U(32.W))
|
||||
io.WB_ACK_O := RegNext((io.RegCs.orR | BDAck) & ~io.WB_ACK_O, false.B)
|
||||
|
||||
} else {
|
||||
io.RegCs := Fill(4, io.slvA.fire & io.slvA.bits.mask.orR & ~io.slvA.bits.address(11) & ~io.slvA.bits.address(10)) & io.slvA.bits.mask // 0x0 - 0x3FF
|
||||
BDCs := Fill(4, io.slvA.fire & io.slvA.bits.mask.orR & ~io.slvA.bits.address(11) & io.slvA.bits.address(10)) & io.slvA.bits.mask // 0x400 - 0x7FF
|
||||
CsMiss := io.slvA.fire & io.slvA.bits.mask.orR & io.slvA.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
|
||||
// } else {
|
||||
// io.RegCs := Fill(4, io.slvA.fire & io.slvA.bits.mask.orR & ~io.slvA.bits.address(11) & ~io.slvA.bits.address(10)) & io.slvA.bits.mask // 0x0 - 0x3FF
|
||||
// BDCs := Fill(4, io.slvA.fire & io.slvA.bits.mask.orR & ~io.slvA.bits.address(11) & io.slvA.bits.address(10)) & io.slvA.bits.mask // 0x400 - 0x7FF
|
||||
// CsMiss := io.slvA.fire & io.slvA.bits.mask.orR & io.slvA.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
|
||||
|
||||
io.WB_DAT_O := RegNext(Mux( ((io.RegCs.orR) & (io.slvA.bits.opcode === 4.U)), io.RegDataOut, BD_WB_DAT_O ), 0.U(32.W))
|
||||
// io.WB_DAT_O := RegNext(Mux( ((io.RegCs.orR) & (io.slvA.bits.opcode === 4.U)), io.RegDataOut, BD_WB_DAT_O ), 0.U(32.W))
|
||||
|
||||
val slvAInfo = RegEnable( io.slvA.bits, io.slvA.fire )
|
||||
val slvDValid = RegInit(false.B); io.slvD.valid := slvDValid
|
||||
when( io.slvD.fire ){
|
||||
slvDValid := false.B
|
||||
} .elsewhen(io.RegCs.orR | BDAck){
|
||||
slvDValid := true.B
|
||||
}
|
||||
// val slvAInfo = RegEnable( io.slvA.bits, io.slvA.fire )
|
||||
// val slvDValid = RegInit(false.B); io.slvD.valid := slvDValid
|
||||
// when( io.slvD.fire ){
|
||||
// slvDValid := false.B
|
||||
// } .elsewhen(io.RegCs.orR | BDAck){
|
||||
// slvDValid := true.B
|
||||
// }
|
||||
|
||||
|
||||
io.slvD.bits :=
|
||||
}
|
||||
// io.slvD.bits :=
|
||||
// }
|
||||
|
||||
|
||||
io.WB_ERR_O := RegNext(io.WB_STB_I & io.WB_CYC_I & (~(io.WB_SEL_I.orR) | CsMiss) & ~io.WB_ERR_O, false.B)
|
||||
|
||||
24
src/main/scala/mac/Parameters.scala
Normal file
24
src/main/scala/mac/Parameters.scala
Normal file
@@ -0,0 +1,24 @@
|
||||
package MAC
|
||||
|
||||
import chisel3._
|
||||
import chisel3.stage._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
case object MacParamsKey extends Field[MacSetting]
|
||||
|
||||
|
||||
case class MacSetting(){
|
||||
|
||||
}
|
||||
|
||||
trait HasMacParameters {
|
||||
implicit val p: Parameters
|
||||
|
||||
val riftSetting = p(MacParamsKey)
|
||||
}
|
||||
|
||||
class MacCfg extends Config((_, _, _) => {
|
||||
case MacParamsKey => MacSetting()
|
||||
})
|
||||
@@ -3,11 +3,27 @@ package test
|
||||
import MAC._
|
||||
import chisel3._
|
||||
import chisel3.stage._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
|
||||
|
||||
object testModule extends App {
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => {
|
||||
// new Mac
|
||||
// })
|
||||
// ))
|
||||
val cfg = new MacCfg
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => {
|
||||
new MacTileLink
|
||||
val soc = LazyModule(new Mac()(cfg))
|
||||
soc.module
|
||||
})
|
||||
))
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user