top layer and some bugs fixed

src/test/scala/gcd/test.scala

@@ -3,11 +3,27 @@ package test
 import MAC._
 import chisel3._
 import chisel3.stage._
+import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.cde.config._
+
+
 
 object testModule extends App {
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
+  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
+  //     ChiselGeneratorAnnotation(() => {
+  //   new Mac
+  // })
+  //   ))
+  val cfg = new MacCfg
+
+  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    new MacTileLink
+    val soc = LazyModule(new Mac()(cfg))
+    soc.module
   })
-    ))
-}
+  ))
+
+
+}
+