This commit is contained in:
RuigeLee
2023-07-12 18:43:28 +08:00
parent 63be80135c
commit 02ec89bda5

View File

@@ -30,11 +30,8 @@ class MacAXI(implicit p: Parameters) extends Mac{
)) ))
memAXI4SlaveNode := memAXI4SlaveNode :=
AXI4UserYanker() :=
AXI4IdIndexer(1) :=
AXI4Deinterleaver(32/8) := AXI4Deinterleaver(32/8) :=
TLToAXI4() := TLToAXI4() :=
TLWidthWidget(32 / 8) :=
tlClientNode tlClientNode
@@ -62,7 +59,7 @@ class MacAXI(implicit p: Parameters) extends Mac{
val xbar = TLXbar() val xbar = TLXbar()
tlMasterNode := xbar := TLFIFOFixer() := TLWidthWidget(32/8) := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := AXI4Buffer() := AXI4IdIndexer(1) := axiConfigPort tlMasterNode := xbar := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := axiConfigPort
tlError.node := xbar tlError.node := xbar
val intSinkNode = IntSinkNode(IntSinkPortSimple()) val intSinkNode = IntSinkNode(IntSinkPortSimple())