axi opt
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@@ -30,11 +30,8 @@ class MacAXI(implicit p: Parameters) extends Mac{
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))
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memAXI4SlaveNode :=
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AXI4UserYanker() :=
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AXI4IdIndexer(1) :=
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AXI4Deinterleaver(32/8) :=
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TLToAXI4() :=
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TLWidthWidget(32 / 8) :=
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tlClientNode
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@@ -62,7 +59,7 @@ class MacAXI(implicit p: Parameters) extends Mac{
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val xbar = TLXbar()
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tlMasterNode := xbar := TLFIFOFixer() := TLWidthWidget(32/8) := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := AXI4Buffer() := AXI4IdIndexer(1) := axiConfigPort
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tlMasterNode := xbar := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := axiConfigPort
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tlError.node := xbar
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val intSinkNode = IntSinkNode(IntSinkPortSimple())
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