Revert "重开ebus项目"

This reverts commit a3234d7f48.

src/main/scala/backBoard/ebus/FSMC.scala.bk

@@ -0,0 +1,42 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+
+
+
+class FSMCSlvIO extends Bundle{
+  val FSMC = new FSMC_Port_Bundle
+
+  val CDRIn  = Flipped(Valid(new CDRData))
+  val CDROut = Valid(new CDRData)
+}
+
+class FSMCSlvBase extends Module{
+  val io: FSMCSlvIO = IO(new FSMCSlvIO)
+
+
+
+
+
+
+
+
+
+
+  mirror.io.datar_b,
+  mirror.io.ce_b,
+  mirror.io.we_b,
+  mirror.io.[10:0] addr_b,
+  mirror.io.[7:0] dataw_b
+}
+
+trait MirrorSRAM { this: FSMCSlvBase =>
+
+
+}
+
+