eb001/tb/verilator/SimTop.v

module SimTop (

	// output success,
	// output fail,

	input clock, //100MHz
	input reset,
  input clk400,

  input  uDatIn,
  output uDatOut,
  input  dDatIn,
  output dDatOut
);







wire dmactive;

ExampleRocketSystem s_rocket(
  .clock(clock),
  .reset(reset),
  .resetctrl_hartIsInReset_0(reset),

  .debug_clock(clock),
  .debug_reset(reset),
  .debug_systemjtag_jtag_TCK(1'b0),
  .debug_systemjtag_jtag_TMS(1'b0),
  .debug_systemjtag_jtag_TDI(1'b0),
  .debug_systemjtag_jtag_TDO_data(),
  .debug_systemjtag_jtag_TDO_driven(),
  .debug_systemjtag_reset(reset),
  .debug_systemjtag_mfr_id(11'b0),
  .debug_systemjtag_part_number(16'b0),
  .debug_systemjtag_version(4'b0),
  .debug_ndreset(),
  .debug_dmactive(dmactive),
  .debug_dmactiveAck(dmactive),

  .mmio_apb_0_psel(),
  .mmio_apb_0_penable(),
  .mmio_apb_0_pwrite(),
  .mmio_apb_0_paddr(),
  .mmio_apb_0_pprot(),
  .mmio_apb_0_pwdata(),
  .mmio_apb_0_pstrb(),
  .mmio_apb_0_pready(1'b1),
  .mmio_apb_0_pslverr(1'b0),
  .mmio_apb_0_prdata(32'b0),

  .mmio_ahb_0_hmastlock(),
  .mmio_ahb_0_hsel(),
  .mmio_ahb_0_hready(),
  .mmio_ahb_0_hreadyout(1'b1),
  .mmio_ahb_0_htrans(),
  .mmio_ahb_0_hsize(),
  .mmio_ahb_0_hburst(),
  .mmio_ahb_0_hwrite(),
  .mmio_ahb_0_hprot(),
  .mmio_ahb_0_haddr(),
  .mmio_ahb_0_hwdata(),
  .mmio_ahb_0_hresp(2'b0),
  .mmio_ahb_0_hrdata(32'b0),
  .mmio_ahb_0_hmaster(),
  .mmio_ahb_0_hsplit(16'b0),

  .interrupts(2'b0),

  .cdrio_overCLK(clk400),
  .cdrio_uDatIn(uDatIn),
  .cdrio_uDatOut(uDatOut),
  .cdrio_dDatIn(dDatIn),
  .cdrio_dDatOut(dDatOut)
);






// wire debugger_success;

// debuger i_debuger(
//   .success(debugger_success),
// 	.DEBUGER_AWID   (mmio_axi4_0_aw_bits_id),
// 	.DEBUGER_BID    (mmio_axi4_0_b_bits_id),
// 	.DEBUGER_ARID   (mmio_axi4_0_ar_bits_id),
// 	.DEBUGER_RID    (mmio_axi4_0_r_bits_id),

// 	.DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
// 	.DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
// 	.DEBUGER_AWREADY(mmio_axi4_0_aw_ready),

// 	.DEBUGER_WDATA (mmio_axi4_0_w_bits_data),   
// 	.DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
// 	.DEBUGER_WVALID(mmio_axi4_0_w_valid),
// 	.DEBUGER_WREADY(mmio_axi4_0_w_ready),

// 	.DEBUGER_BRESP (mmio_axi4_0_b_bits_resp),
// 	.DEBUGER_BVALID(mmio_axi4_0_b_valid),
// 	.DEBUGER_BREADY(mmio_axi4_0_b_ready),

// 	.DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
// 	.DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
// 	.DEBUGER_ARREADY(mmio_axi4_0_ar_ready),

// 	.DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
// 	.DEBUGER_RRESP (mmio_axi4_0_r_bits_resp),
// 	.DEBUGER_RVALID(mmio_axi4_0_r_valid),
// 	.DEBUGER_RREADY(mmio_axi4_0_r_ready),

// 	.CLK(CLK),
// 	.RSTn(RSTn)
	
// );




    
	// reg [1023:0] firmware_file;
	// initial begin
	// 	if ($value$plusargs("%s", firmware_file)) begin
	// 		$display("%s", firmware_file);
	// 		$readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
	// 	end
	// end








// assign success = debugger_success;




string testName;

`define MEM s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram
reg [7:0] mem [0:200000];

localparam DP = 8192;
integer i;
initial begin

#20

	if ( $value$plusargs("%s",testName) ) begin
		$display("%s",testName);
	  $readmemh(testName, mem);		
	end
	else begin 
    $display("%s",testName);
		$error("Failed to read Files!");
	end

	
	for ( i = 0; i < DP; i = i + 1 ) begin
    if ( mem[i*4+0] || mem[i*4+1] || mem[i*4+2] || mem[i*4+3] ) begin
      `MEM[i] = {mem[i*4+3], mem[i*4+2], mem[i*4+1], mem[i*4+0]};


      $display("%x",`MEM[i]);
    end
    else begin
      `MEM[i][7:0]   = 8'h0;
      `MEM[i][15:8]  = 8'h0;
      `MEM[i][23:16] = 8'h0;
      `MEM[i][31:24] = 8'h0;
    end
	end
end 

wire [31:0] test1 = `MEM[0];
wire [31:0] test2 = `MEM[1];
wire [31:0] test3 = `MEM[2];
wire [31:0] test4 = `MEM[3];



endmodule