2025-01-15 11:23:02 +08:00
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#include <stdint.h>
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#include "tl2cdr.h"
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#ifndef TL2CDR_BASE
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#error TL2CDR Base address not define!!!
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#endif
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2025-02-09 01:17:17 +08:00
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#ifdef OLD_CODE
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2025-02-03 23:49:50 +08:00
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volatile uint32_t * const cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
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volatile uint32_t * const cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
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volatile uint32_t * const cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
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volatile uint32_t * const cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
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2025-01-15 11:23:02 +08:00
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2025-02-03 23:49:50 +08:00
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volatile uint32_t * const cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
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volatile uint32_t * const cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
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volatile uint32_t * const cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
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2025-01-15 11:23:02 +08:00
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2025-02-03 23:49:50 +08:00
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volatile uint32_t * const cdr_IsLast = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
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volatile uint32_t * const cdr_rxCrc = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
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volatile uint32_t * const cdr_txCrc = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
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#endif
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2025-01-15 11:23:02 +08:00
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2025-02-09 01:17:17 +08:00
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volatile uint32_t * const tx0_softReset = (uint32_t*)( TL2CDR_BASE + TX0_WriteSoftReset );
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volatile uint32_t * const tx0_txLen = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxLen );
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volatile uint32_t * const tx0_txFifo = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxFifo );
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volatile uint32_t * const tx0_txCrc = (uint32_t*)( TL2CDR_BASE + TX0_ReadTxCrc );
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volatile uint32_t * const tx1_softReset = (uint32_t*)( TL2CDR_BASE + TX1_WriteSoftReset );
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volatile uint32_t * const tx1_txLen = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxLen );
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volatile uint32_t * const tx1_txFifo = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxFifo );
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volatile uint32_t * const tx1_txCrc = (uint32_t*)( TL2CDR_BASE + TX1_ReadTxCrc );
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volatile uint32_t * const rx0_softReset = (uint32_t*)( TL2CDR_BASE + RX0_WriteSoftReset );
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volatile uint32_t * const rx0_rxLen = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxLen );
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volatile uint32_t * const rx0_rxFifo = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxFifo );
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volatile uint32_t * const rx0_rxCrc = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxCrc );
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volatile uint32_t * const rx0_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX0_WrtieLimitTimerAim );
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volatile uint32_t * const rx0_rxTxPair = (uint32_t*)( TL2CDR_BASE + RX0_WriteLimitTxPair );
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volatile uint32_t * const rx1_softReset = (uint32_t*)( TL2CDR_BASE + RX1_WriteSoftReset );
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volatile uint32_t * const rx1_rxLen = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxLen );
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volatile uint32_t * const rx1_rxFifo = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxFifo );
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volatile uint32_t * const rx1_rxCrc = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxCrc );
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volatile uint32_t * const rx1_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX1_WrtieLimitTimerAim );
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volatile uint32_t * const rx1_rxTxPair = (uint32_t*)( TL2CDR_BASE + RX1_WriteLimitTxPair );
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volatile uint32_t * const HLM_status = (uint32_t*)( TL2CDR_BASE + HLM_ReadStatus );
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volatile uint32_t * const HLM_isLast = (uint32_t*)( TL2CDR_BASE + HLM_ReadIsLast );
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