55 lines
1.2 KiB
Coq
55 lines
1.2 KiB
Coq
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/*
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Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`timescale 1 ns / 1 ps
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module gen_slffr # (
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parameter DW = 1,
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parameter rstValue = 1'b0
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)
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(
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input [DW-1:0] set_in,
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input [DW-1:0] rst_in,
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output [DW-1:0] qout,
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input CLK,
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input RSTn
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);
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wire [DW-1:0] rsffr_qout;
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gen_rsffr # ( .DW(DW), .rstValue(rstValue)) rsffr ( .set_in(set_in), .rst_in(rst_in), .qout(rsffr_qout), .CLK(CLK), .RSTn(RSTn));
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assign qout = set_in | rsffr_qout;
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//ASSERT
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always @( posedge CLK ) begin
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if ( set_in & rst_in ) begin
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$display("Assert Fail at gen_slff");
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$finish;
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end
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end
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endmodule
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