317 lines
15 KiB
Coq
317 lines
15 KiB
Coq
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module FPGATop(
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input clock,
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input reset,
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(* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TCK" *)
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input debug_systemjtag_jtag_TCK,
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(* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TMS" *)
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input debug_systemjtag_jtag_TMS,
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(* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TD_I" *)
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input debug_systemjtag_jtag_TDI,
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(* X_INTERFACE_INFO = "xilinx.com:interface:jtag:1.0 JTAG TD_O" *)
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output debug_systemjtag_jtag_TDO_data,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWREADY" *)
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input mem_axi4_0_aw_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWVALID" *)
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output mem_axi4_0_aw_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWID" *)
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output [3:0] mem_axi4_0_aw_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWADDR" *)
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output [31:0] mem_axi4_0_aw_bits_addr,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWLEN" *)
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output [7:0] mem_axi4_0_aw_bits_len,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWSIZE" *)
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output [2:0] mem_axi4_0_aw_bits_size,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWBURST" *)
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output [1:0] mem_axi4_0_aw_bits_burst,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWLOCK" *)
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output mem_axi4_0_aw_bits_lock,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWCACHE" *)
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output [3:0] mem_axi4_0_aw_bits_cache,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWPROT" *)
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output [2:0] mem_axi4_0_aw_bits_prot,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem AWQOS" *)
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output [3:0] mem_axi4_0_aw_bits_qos,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WREADY" *)
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input mem_axi4_0_w_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WVALID" *)
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output mem_axi4_0_w_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WDATA" *)
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output [31:0] mem_axi4_0_w_bits_data,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WSTRB" *)
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output [3:0] mem_axi4_0_w_bits_strb,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem WLAST" *)
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output mem_axi4_0_w_bits_last,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BREADY" *)
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output mem_axi4_0_b_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BVALID" *)
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input mem_axi4_0_b_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BID" *)
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input [3:0] mem_axi4_0_b_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem BRESP" *)
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input [1:0] mem_axi4_0_b_bits_resp,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARREADY" *)
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input mem_axi4_0_ar_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARVALID" *)
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output mem_axi4_0_ar_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARID" *)
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output [3:0] mem_axi4_0_ar_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARADDR" *)
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output [31:0] mem_axi4_0_ar_bits_addr,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARLEN" *)
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output [7:0] mem_axi4_0_ar_bits_len,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARSIZE" *)
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output [2:0] mem_axi4_0_ar_bits_size,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARBURST" *)
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output [1:0] mem_axi4_0_ar_bits_burst,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARLOCK" *)
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output mem_axi4_0_ar_bits_lock,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARCACHE" *)
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output [3:0] mem_axi4_0_ar_bits_cache,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARPROT" *)
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output [2:0] mem_axi4_0_ar_bits_prot,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem ARQOS" *)
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output [3:0] mem_axi4_0_ar_bits_qos,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RREADY" *)
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output mem_axi4_0_r_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RVALID" *)
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input mem_axi4_0_r_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RID" *)
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input [3:0] mem_axi4_0_r_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RDATA" *)
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input [31:0] mem_axi4_0_r_bits_data,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RRESP" *)
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input [1:0] mem_axi4_0_r_bits_resp,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mem RLAST" *)
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input mem_axi4_0_r_bits_last,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWREADY" *)
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input mmio_axi4_0_aw_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWVALID" *)
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output mmio_axi4_0_aw_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWID" *)
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output [3:0] mmio_axi4_0_aw_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWADDR" *)
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output [30:0] mmio_axi4_0_aw_bits_addr,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWLEN" *)
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output [7:0] mmio_axi4_0_aw_bits_len,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWSIZE" *)
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output [2:0] mmio_axi4_0_aw_bits_size,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWBURST" *)
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output [1:0] mmio_axi4_0_aw_bits_burst,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWLOCK" *)
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output mmio_axi4_0_aw_bits_lock,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWCACHE" *)
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output [3:0] mmio_axi4_0_aw_bits_cache,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWPROT" *)
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output [2:0] mmio_axi4_0_aw_bits_prot,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio AWQOS" *)
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output [3:0] mmio_axi4_0_aw_bits_qos,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WREADY" *)
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input mmio_axi4_0_w_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WVALID" *)
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output mmio_axi4_0_w_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WDATA" *)
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output [31:0] mmio_axi4_0_w_bits_data,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WSTRB" *)
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output [3:0] mmio_axi4_0_w_bits_strb,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio WLAST" *)
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output mmio_axi4_0_w_bits_last,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BREADY" *)
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output mmio_axi4_0_b_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BVALID" *)
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input mmio_axi4_0_b_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BID" *)
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input [3:0] mmio_axi4_0_b_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio BRESP" *)
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input [1:0] mmio_axi4_0_b_bits_resp,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARREADY" *)
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input mmio_axi4_0_ar_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARVALID" *)
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output mmio_axi4_0_ar_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARID" *)
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output [3:0] mmio_axi4_0_ar_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARADDR" *)
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output [30:0] mmio_axi4_0_ar_bits_addr,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARLEN" *)
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output [7:0] mmio_axi4_0_ar_bits_len,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARSIZE" *)
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output [2:0] mmio_axi4_0_ar_bits_size,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARBURST" *)
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output [1:0] mmio_axi4_0_ar_bits_burst,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARLOCK" *)
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output mmio_axi4_0_ar_bits_lock,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARCACHE" *)
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output [3:0] mmio_axi4_0_ar_bits_cache,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARPROT" *)
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output [2:0] mmio_axi4_0_ar_bits_prot,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio ARQOS" *)
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output [3:0] mmio_axi4_0_ar_bits_qos,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RREADY" *)
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output mmio_axi4_0_r_ready,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RVALID" *)
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input mmio_axi4_0_r_valid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RID" *)
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input [3:0] mmio_axi4_0_r_bits_id,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RDATA" *)
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input [31:0] mmio_axi4_0_r_bits_data,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RRESP" *)
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input [1:0] mmio_axi4_0_r_bits_resp,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 mmio RLAST" *)
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input mmio_axi4_0_r_bits_last,
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output macIO_mdc,
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inout mdio,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII TX_CLK" *)
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input macIO_mtx_clk_pad_i,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII TXD" *)
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output [3:0] macIO_mtxd_pad_o,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII TX_EN" *)
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output macIO_mtxen_pad_o,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RX_CLK" *)
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input macIO_mrx_clk_pad_i,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RXD" *)
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input [3:0] macIO_mrxd_pad_i,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RX_DV" *)
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input macIO_mrxdv_pad_i,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII RX_ER" *)
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input macIO_mrxerr_pad_i,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII COL" *)
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input macIO_mcoll_pad_i,
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(* X_INTERFACE_INFO = "xilinx.com:interface:mii:1.0 MII CRS" *)
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input macIO_mcrs_pad_i
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);
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wire active;
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wire mdi;
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wire mdo;
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wire mdoEn;
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ExampleRocketSystem i_rocketChip(
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.clock(clock),
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.reset(reset),
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.resetctrl_hartIsInReset_0(reset),
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.debug_clock(clock),
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.debug_reset(reset),
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.debug_systemjtag_jtag_TCK(debug_systemjtag_jtag_TCK),
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.debug_systemjtag_jtag_TMS(debug_systemjtag_jtag_TMS),
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.debug_systemjtag_jtag_TDI(debug_systemjtag_jtag_TDI),
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.debug_systemjtag_jtag_TDO_data(debug_systemjtag_jtag_TDO_data),
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.debug_systemjtag_jtag_TDO_driven(),
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.debug_systemjtag_reset(reset),
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.debug_systemjtag_mfr_id(11'b0),
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.debug_systemjtag_part_number(16'b0),
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.debug_systemjtag_version(4'b0),
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.debug_ndreset(),
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.debug_dmactive(active),
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.debug_dmactiveAck(active),
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.mem_axi4_0_aw_ready(mem_axi4_0_aw_ready),
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.mem_axi4_0_aw_valid(mem_axi4_0_aw_valid),
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.mem_axi4_0_aw_bits_id(mem_axi4_0_aw_bits_id),
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.mem_axi4_0_aw_bits_addr(mem_axi4_0_aw_bits_addr),
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.mem_axi4_0_aw_bits_len(mem_axi4_0_aw_bits_len),
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.mem_axi4_0_aw_bits_size(mem_axi4_0_aw_bits_size),
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.mem_axi4_0_aw_bits_burst(mem_axi4_0_aw_bits_burst),
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.mem_axi4_0_aw_bits_lock(mem_axi4_0_aw_bits_lock),
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.mem_axi4_0_aw_bits_cache(mem_axi4_0_aw_bits_cache),
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.mem_axi4_0_aw_bits_prot(mem_axi4_0_aw_bits_prot),
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.mem_axi4_0_aw_bits_qos(mem_axi4_0_aw_bits_qos),
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.mem_axi4_0_w_ready(mem_axi4_0_w_ready),
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.mem_axi4_0_w_valid(mem_axi4_0_w_valid),
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.mem_axi4_0_w_bits_data(mem_axi4_0_w_bits_data),
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.mem_axi4_0_w_bits_strb(mem_axi4_0_w_bits_strb),
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.mem_axi4_0_w_bits_last(mem_axi4_0_w_bits_last),
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.mem_axi4_0_b_ready(mem_axi4_0_b_ready),
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.mem_axi4_0_b_valid(mem_axi4_0_b_valid),
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.mem_axi4_0_b_bits_id(mem_axi4_0_b_bits_id),
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.mem_axi4_0_b_bits_resp(mem_axi4_0_b_bits_resp),
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.mem_axi4_0_ar_ready(mem_axi4_0_ar_ready),
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.mem_axi4_0_ar_valid(mem_axi4_0_ar_valid),
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||
|
|
.mem_axi4_0_ar_bits_id(mem_axi4_0_ar_bits_id),
|
||
|
|
.mem_axi4_0_ar_bits_addr(mem_axi4_0_ar_bits_addr),
|
||
|
|
.mem_axi4_0_ar_bits_len(mem_axi4_0_ar_bits_len),
|
||
|
|
.mem_axi4_0_ar_bits_size(mem_axi4_0_ar_bits_size),
|
||
|
|
.mem_axi4_0_ar_bits_burst(mem_axi4_0_ar_bits_burst),
|
||
|
|
.mem_axi4_0_ar_bits_lock(mem_axi4_0_ar_bits_lock),
|
||
|
|
.mem_axi4_0_ar_bits_cache(mem_axi4_0_ar_bits_cache),
|
||
|
|
.mem_axi4_0_ar_bits_prot(mem_axi4_0_ar_bits_prot),
|
||
|
|
.mem_axi4_0_ar_bits_qos(mem_axi4_0_ar_bits_qos),
|
||
|
|
.mem_axi4_0_r_ready(mem_axi4_0_r_ready),
|
||
|
|
.mem_axi4_0_r_valid(mem_axi4_0_r_valid),
|
||
|
|
.mem_axi4_0_r_bits_id(mem_axi4_0_r_bits_id),
|
||
|
|
.mem_axi4_0_r_bits_data(mem_axi4_0_r_bits_data),
|
||
|
|
.mem_axi4_0_r_bits_resp(mem_axi4_0_r_bits_resp),
|
||
|
|
.mem_axi4_0_r_bits_last(mem_axi4_0_r_bits_last),
|
||
|
|
|
||
|
|
.mmio_axi4_0_aw_ready(mmio_axi4_0_aw_ready),
|
||
|
|
.mmio_axi4_0_aw_valid(mmio_axi4_0_aw_valid),
|
||
|
|
.mmio_axi4_0_aw_bits_id(mmio_axi4_0_aw_bits_id),
|
||
|
|
.mmio_axi4_0_aw_bits_addr(mmio_axi4_0_aw_bits_addr),
|
||
|
|
.mmio_axi4_0_aw_bits_len(mmio_axi4_0_aw_bits_len),
|
||
|
|
.mmio_axi4_0_aw_bits_size(mmio_axi4_0_aw_bits_size),
|
||
|
|
.mmio_axi4_0_aw_bits_burst(mmio_axi4_0_aw_bits_burst),
|
||
|
|
.mmio_axi4_0_aw_bits_lock(mmio_axi4_0_aw_bits_lock),
|
||
|
|
.mmio_axi4_0_aw_bits_cache(mmio_axi4_0_aw_bits_cache),
|
||
|
|
.mmio_axi4_0_aw_bits_prot(mmio_axi4_0_aw_bits_prot),
|
||
|
|
.mmio_axi4_0_aw_bits_qos(mmio_axi4_0_aw_bits_qos),
|
||
|
|
.mmio_axi4_0_w_ready(mmio_axi4_0_w_ready),
|
||
|
|
.mmio_axi4_0_w_valid(mmio_axi4_0_w_valid),
|
||
|
|
.mmio_axi4_0_w_bits_data(mmio_axi4_0_w_bits_data),
|
||
|
|
.mmio_axi4_0_w_bits_strb(mmio_axi4_0_w_bits_strb),
|
||
|
|
.mmio_axi4_0_w_bits_last(mmio_axi4_0_w_bits_last),
|
||
|
|
.mmio_axi4_0_b_ready(mmio_axi4_0_b_ready),
|
||
|
|
.mmio_axi4_0_b_valid(mmio_axi4_0_b_valid),
|
||
|
|
.mmio_axi4_0_b_bits_id(mmio_axi4_0_b_bits_id),
|
||
|
|
.mmio_axi4_0_b_bits_resp(mmio_axi4_0_b_bits_resp),
|
||
|
|
.mmio_axi4_0_ar_ready(mmio_axi4_0_ar_ready),
|
||
|
|
.mmio_axi4_0_ar_valid(mmio_axi4_0_ar_valid),
|
||
|
|
.mmio_axi4_0_ar_bits_id(mmio_axi4_0_ar_bits_id),
|
||
|
|
.mmio_axi4_0_ar_bits_addr(mmio_axi4_0_ar_bits_addr),
|
||
|
|
.mmio_axi4_0_ar_bits_len(mmio_axi4_0_ar_bits_len),
|
||
|
|
.mmio_axi4_0_ar_bits_size(mmio_axi4_0_ar_bits_size),
|
||
|
|
.mmio_axi4_0_ar_bits_burst(mmio_axi4_0_ar_bits_burst),
|
||
|
|
.mmio_axi4_0_ar_bits_lock(mmio_axi4_0_ar_bits_lock),
|
||
|
|
.mmio_axi4_0_ar_bits_cache(mmio_axi4_0_ar_bits_cache),
|
||
|
|
.mmio_axi4_0_ar_bits_prot(mmio_axi4_0_ar_bits_prot),
|
||
|
|
.mmio_axi4_0_ar_bits_qos(mmio_axi4_0_ar_bits_qos),
|
||
|
|
.mmio_axi4_0_r_ready(mmio_axi4_0_r_ready),
|
||
|
|
.mmio_axi4_0_r_valid(mmio_axi4_0_r_valid),
|
||
|
|
.mmio_axi4_0_r_bits_id(mmio_axi4_0_r_bits_id),
|
||
|
|
.mmio_axi4_0_r_bits_data(mmio_axi4_0_r_bits_data),
|
||
|
|
.mmio_axi4_0_r_bits_resp(mmio_axi4_0_r_bits_resp),
|
||
|
|
.mmio_axi4_0_r_bits_last(mmio_axi4_0_r_bits_last),
|
||
|
|
.interrupts(2'b0),
|
||
|
|
.macIO_mdi(mdi),
|
||
|
|
.macIO_mdc(macIO_mdc),
|
||
|
|
.macIO_mdo(mdo),
|
||
|
|
.macIO_mdoEn(mdoEn),
|
||
|
|
.macIO_mtx_clk_pad_i(macIO_mtx_clk_pad_i),
|
||
|
|
.macIO_mtxd_pad_o(macIO_mtxd_pad_o),
|
||
|
|
.macIO_mtxen_pad_o(macIO_mtxen_pad_o),
|
||
|
|
.macIO_mtxerr_pad_o(),
|
||
|
|
.macIO_mrx_clk_pad_i(macIO_mrx_clk_pad_i),
|
||
|
|
.macIO_mrxd_pad_i(macIO_mrxd_pad_i),
|
||
|
|
.macIO_mrxdv_pad_i(macIO_mrxdv_pad_i),
|
||
|
|
.macIO_mrxerr_pad_i(macIO_mrxerr_pad_i),
|
||
|
|
.macIO_mcoll_pad_i(macIO_mcoll_pad_i),
|
||
|
|
.macIO_mcrs_pad_i(macIO_mcrs_pad_i)
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
IOBUF #(
|
||
|
|
.DRIVE(12), // Specify the output drive strength
|
||
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
||
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
||
|
|
.SLEW("SLOW") // Specify the output slew rate
|
||
|
|
) IOBUF_inst (
|
||
|
|
.O(mdi), // Buffer output
|
||
|
|
.IO(mdio), // Buffer inout port (connect directly to top-level port)
|
||
|
|
.I(mdo), // Buffer input
|
||
|
|
.T(mdoEn) // 3-state enable input, high=input, low=output
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|