98 lines
1.6 KiB
Coq
98 lines
1.6 KiB
Coq
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/*
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Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`timescale 1 ns / 1 ps
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module gen_sram #
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(
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parameter DW = 32,
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parameter AW = 14
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)
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(
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input [DW-1:0] data_w,
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input [AW-1:0] addr_w,
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input [(DW+7)/8-1:0] data_wstrb,
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input en_w,
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output [DW-1:0] data_r,
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input [AW-1:0] addr_r,
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input en_r,
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input CLK
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);
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localparam DP = 2**AW;
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localparam DW_ZM = (DW+7)/8*8;
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reg [DW_ZM-1:0] ram[0:DP-1];
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reg [DW_ZM-1:0] data_r_reg;
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wire [DW_ZM-1:0] data_w_zmask = {DW_ZM{1'b0}} | data_w;
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generate
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for ( genvar i = 0; i < (DW+7)/8; i = i + 1) begin
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always @(posedge CLK) begin
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if (en_w) begin
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if (data_wstrb[i]) begin
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ram[addr_w][i*8+:8] <= #1 data_w_zmask[i*8+:8] ;
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end
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end
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if (en_r) begin
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data_r_reg[i*8+:8] <= #1 ram[addr_r][i*8+:8];
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end
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end
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end
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endgenerate
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assign data_r = data_r_reg[DW-1:0];
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// integer i;
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// initial begin
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// for ( i = 0; i < DP; i = i + 1 ) begin
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// ram[i] = {((DW+31)/32){$random}};
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// end
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// data_r_reg = {((DW+31)/32){$random}};
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// end
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endmodule
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