55 lines
1.2 KiB
Scala
55 lines
1.2 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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class ShinTopIO extends Bundle{
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val clk8x = Input(Bool())
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val modeSel = Input(Bool())\
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val qspi =
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val interrupt = Output(Bool())
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val ctrl = Input(UInt(4.W))
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}
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class ShinTop extends Module{
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val io: ShinTopIO = IO(new ShinTopIO)
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val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
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val slaveParser = Module(new SlaveParser )
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val masterParser = Module(new MasterParser)
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val sram = Module(new ShareSRAMDP)
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val interface = Module(new Interface)
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sram.io.addrA := Input(UInt(15.W))
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sram.io.datawA := Input( UInt(8.W) )
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sram.io.datarA := Output( UInt(8.W) )
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sram.io.enwA := Input(Bool())
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sram.io.enrA := Input(Bool())
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sram.io.clockA := Input(Bool())
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sram.io.addrB := Input(UInt(15.W))
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sram.io.datawB := Input( UInt(8.W) )
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sram.io.datarB := Output( UInt(8.W) )
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sram.io.enwB := Input(Bool())
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sram.io.enrB := Input(Bool())
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sram.io.clockB := Input(Bool())
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}
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