86 lines
2.0 KiB
Scala
86 lines
2.0 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
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class ShareSRAMDPIO extends Bundle{
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val addrA = Input(UInt(15.W))
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val datawA = Input( UInt(8.W) )
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val datarA = Output( UInt(8.W) )
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val enwA = Input(Bool())
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val enrA = Input(Bool())
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val clockA = Input(Bool())
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val addrB = Input(UInt(15.W))
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val datawB = Input( UInt(8.W) )
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val datarB = Output( UInt(8.W) )
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val enwB = Input(Bool())
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val enrB = Input(Bool())
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val clockB = Input(Bool())
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}
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val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
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setInline("MirrorSRAMDP.v",
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"""
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| module MirrorSRAMDP(
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| input [7:0] datawA,
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| input [14:0] addrA,
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| input enwA,
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| input enrA,
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| output [7:0] datarA,
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| input clockA,
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| input [7:0] datawB,
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| input [14:0] addrB,
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| input enwB,
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| input enrB,
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| output [7:0] datarB,
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| input clockB
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| );
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| reg [7:0] mem[0:32767];
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| reg [7:0] data_outa_reg = 8'b0;
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| reg [7:0] data_outb_reg = 8'b0;
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| assign datarA = data_outa_reg;
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| assign datarB = data_outb_reg;
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| always@( posedge clockA ) begin
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| if( enrA ) begin
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| end
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| if( enwA ) begin
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| mem[addrA] <= datawA;
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| end else begin
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| data_outa_reg <= mem[addrA];
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| end
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| end
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| always@( posedge clockB ) begin
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| if(enrB) begin
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| end
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| if( enwB ) begin
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| mem[addrB] <= datawB;
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| end else begin
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| data_outb_reg <= mem[addrB];
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| end
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| end
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| initial begin
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| for( integer i = 0; i < 32768; i = i + 1 ) begin
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| mem[i] = $random;
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| end
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| end
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|endmodule
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""".stripMargin)
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}
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