eb001/src/main/scala/backBoard/pico/picorv32.scala

package BACK

import chisel3._
import chisel3.util._
import chisel3.experimental._




class Picorv32 extends BlackBox() with HasBlackBoxResource {
  val io = IO(new Bundle {
	val clk = Input(Bool())
    val resetn = Input(Bool())
	val trap = Output(Bool())

	val mem_valid = Output(Bool())
	val mem_instr = Output(Bool())
	val mem_ready = Input(Bool())

	val mem_addr  = Output(UInt(32.W))
	val mem_wdata = Output(UInt(32.W))
	val mem_wstrb = Output(UInt(4.W))
	val mem_rdata = Input(UInt(32.W))

	// Look-Ahead Interface
	val mem_la_read  = Output(Bool())
	val mem_la_write = Output(Bool())
	val mem_la_addr  = Output(UInt(32.W))
	val mem_la_wdata = Output(UInt(32.W))
	val mem_la_wstrb = Output(UInt(4.W))

	// Pico Co-Processor Interface (PCPI)
	val pcpi_valid = Output(Bool())
	val pcpi_insn  = Output(UInt(32.W))
	val pcpi_rs1   = Output(UInt(32.W))
	val pcpi_rs2   = Output(UInt(32.W))
	val pcpi_wr    = Input(Bool())
	val pcpi_rd    = Input(UInt(32.W))
	val pcpi_wait  = Input(Bool())
	val pcpi_ready = Input(Bool())

	// IRQ Interface
	val irq = Input(UInt(32.W))
	val eoi = Output(UInt(32.W))

	// Trace Interface
	val trace_valid = Output(Bool())
	val trace_data  = Output(UInt(36.W))
  })
  addResource("./picorv32.v")
}

class picorv32_tl extends Module{
  val io = IO(new Bundle {

    val trap = Output(Bool())

    val mem_valid = Output(Bool())
    val mem_instr = Output(Bool())
    val mem_ready = Input(Bool())

    val mem_addr  = Output(UInt(32.W))
    val mem_wdata = Output(UInt(32.W))
    val mem_wstrb = Output(UInt(4.W))
    val mem_rdata = Input(UInt(32.W))


    // IRQ Interface
    val irq = Input(UInt(32.W))
    val eoi = Output(UInt(32.W))

  })


  val core = Module(new Picorv32)

	core.io.clk := clock.asBool
  core.io.resetn := ~reset.asBool
	io.trap := core.io.trap 

	io.mem_valid := core.io.mem_valid
	io.mem_instr := core.io.mem_instr
	core.io.mem_ready := io.mem_ready

	io.mem_addr := core.io.mem_addr
	io.mem_wdata:= core.io.mem_wdata
	io.mem_wstrb:= core.io.mem_wstrb
	core.io.mem_rdata := io.mem_rdata



	// Pico Co-Processor Interface (PCPI)
	core.io.pcpi_wr    := false.B
	core.io.pcpi_rd    := 0.U
	core.io.pcpi_wait  := false.B
	core.io.pcpi_ready := true.B

	// IRQ Interface
	core.io.irq := io.irq
	io.eoi := core.io.eoi

}