eb001/src/main/scala/backBoard/SpiSlv.scala

package BACK

import chisel3._
import chisel3.util._


trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>

  def page: Int

  val sck = Wire(Bool())
  val mosi = Wire(Bool())
  val csn   = Wire(Bool())
  val clk100M = Wire(Bool())

  val localReg = Module(new MirrorSRAMSpi)
  localReg.io.clockw := clock.asBool
  localReg.io.clockr := clock.asBool
  localReg.io.addrr := statusPage
  localReg.io.enr   := true.B

  val localUpdate = RegInit(0.U(16.W))



  val shiftSCK  = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
  val shiftCSn  = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
  val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }


  val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
  val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)


  val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt((8*31).W)) }
  val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
  val pageSel = cmd_100M(7,4)
  val spiCmd  = cmd_100M(3,0)


  val cnt_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(4.W)) }


  withClockAndReset( clk100M.asClock, reset ){//100M

    when( shiftCSn(2) & ~shiftCSn(1) ){
      cnt_100M := 0.U
      // misoReg := false.B
    } .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M < 8.U ){
      cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
      cnt_100M := cnt_100M + 1.U
    } .elsewhen( isSckNegedge & ~shiftCSn(1) & cnt_100M === 8.U ){
      exReg_100M := Mux( spiCmd.extract(1), Cat( localUpdate, 0.U((8*29).W) ), localReg.io.datar )
      cnt_100M := cnt_100M + 1.U
    } .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M === 9.U ){
      // misoReg := exReg_100M.extract(exReg_100M.getWidth-1)
      exReg_100M := Cat( exReg_100M(exReg_100M.getWidth-2 ,0), shiftMOSI(1) )
    }
  }
}


class SpiSlv extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSpiSlv{

  def page: Int = 1

  val spi = IO(new Bundle{
    val sck  = Input(Bool())
    val mosi = Input(Bool())
    val miso = Output(Bool())
    val csn  = Input(Bool())
  })
  val clk100MIO = IO(Input(Bool()))

  sck  := spi.sck
  mosi := spi.mosi
  csn  := spi.csn
  spi.miso := exReg_100M.extract(exReg_100M.getWidth-1)
  clk100M := clk100MIO

  val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)



  when( isCrcPass ){
    localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
  } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 3.U ){
    localUpdate := localUpdate & (~exReg_100M(15,0))
  }
  






  // for( i <- 0 until page ){

    when( isCrcPass ){
      localReg.io.addrw := downRegTemp(0)(3,0)
      localReg.io.enw   := true.B
      localReg.io.dataw := Cat( (1 until 32).map{ i => downRegTemp(i) }.reverse )
    } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 1.U ){
      localReg.io.addrw := pageSel
      localReg.io.enw   := true.B
      localReg.io.dataw := exReg_100M
    } .otherwise{
      localReg.io.addrw := DontCare
      localReg.io.enw   := false.B
      localReg.io.dataw := DontCare
    }



    for( i <- 0 until 31 ) {
      upReg(i+1) := localReg.io.datar((30-i)*8+7, (30-i)*8)
    }


}