eb001/src/main/verilog/di16_top.v

module di16_top(

  input clock, 
     
  input  lvds_up_din_p,
  input  lvds_up_din_n, 
  output lvds_up_dout_p,
  output lvds_up_dout_n,  
           
  input  lvds_down_din_p,
  input  lvds_down_din_n,  
  output lvds_down_dout_p,
  output lvds_down_dout_n,

  output isOnline,
  input  isLast,
  input  DCIn,

  output        LED_PR,
  input  [15:0] in

);

wire resetn = 1'b1;

wire clk_400m;
wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;

wire lock_o;
wire reset_stop;
wire reset_calib;

reg rst_n;
reg rstn_d;




always@(posedge clk_10m_a) begin
  rstn_d <= resetn;
	rst_n <= rstn_d;
end

Gowin_PLLO Gowin_PLLO(
  .lock(lock_o), 
  .clkouta(clk_400m),
  .clkin(clock)
);



TLVDS_OBUF lvds_downstream_out(
  .O(lvds_down_dout_p),
  .OB(lvds_down_dout_n),
  .I(lvds_down_dout)
);


TLVDS_IBUF lvds_downstream_in(
  .O(lvds_down_din),
  .I(lvds_down_din_p),
  .IB(lvds_down_din_n)
);


TLVDS_OBUF lvds_upstream_out(
  .O(lvds_up_dout_p),
  .OB(lvds_up_dout_n),
  .I(lvds_up_dout)
);


TLVDS_IBUF lvds_upstream_in(
  .O(lvds_up_din),
  .I(lvds_up_din_p),
  .IB(lvds_up_din_n)
);


DHCEN dhcen_inst2 (
  .CLKIN(clk_400m),
  .CE(reset_stop),
  .CLKOUT(clk_400m_a)
);


//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
  .rst_n(rst_n),
  .pll_lock(lock_o), // trigged by PLL Lock
  .reset_stop(reset_stop), // for DHCEN CE
  .reset_calib(reset_calib), // for IDES and CLKDIV reset
  .set_calib(), 
  .ready()
);


defparam Inst4_CLKDIVC.DIV_MODE="4";
defparam Inst4_CLKDIVC.GSREN="false";
CLKDIV Inst4_CLKDIVC(
  .RESETN (~reset_calib),
  .HCLKIN (clk_400m_a),
  .CALIB  (1'b0     ),
  .CLKOUT (clk_100m_a)
);


defparam Inst2_CLKDIVC.DIV_MODE="2";
defparam Inst2_CLKDIVC.GSREN="false";
CLKDIV Inst2_CLKDIVC(
  .RESETN (~reset_calib),
  .HCLKIN (clk_100m_a),
  .CALIB  (1'b0     ),
  .CLKOUT (clk_50m_a)
);


defparam Inst5_CLKDIVC.DIV_MODE="5";
defparam Inst5_CLKDIVC.GSREN="false";
CLKDIV Inst5_CLKDIVC(
  .RESETN (~reset_calib),
  .HCLKIN (clk_50m_a),
  .CALIB  (1'b0     ),
  .CLKOUT (clk_10m_a)
);

DIn16 i_din16(
  .reset(~rst_n),
  .clock(clk_10m_a),
  .io_reset_calib(reset_calib),
  .io_oser_pclk(clk_10m_a),
  .io_oser_fclk(clk_50m_a),
  .io_ides_pclk(clk_100m_a),
  .io_ides_fclk(clk_400m_a),

  .io_lvds_down_din(lvds_down_din),
  .io_lvds_down_dout(lvds_down_dout),
  .io_lvds_up_din(lvds_up_din),
  .io_lvds_up_dout(lvds_up_dout),

  .io_isOnline(isOnline),
  .io_isLast(isLast),
  .io_DCIn(DCIn),

  .param_vendorID(`VENDORID),
  .param_moduleID(`MODULEID),
  .param_hwVersion(`HWVERSION),
  .param_swVersion(`SWVERSION),
  .param_batchID(`BATCHID),
  .param_serial(`SERIAL),
  .LED_PR(LED_PR),
  .in(in)
);

endmodule