2025-04-24 16:18:33 +08:00
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package BACK
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2025-04-02 16:40:25 +08:00
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2025-04-24 16:18:33 +08:00
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import chisel3._
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import chisel3.util._
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2025-04-02 16:40:25 +08:00
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2025-08-26 17:52:23 +08:00
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import chisel3.experimental.dataview._
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2025-08-26 17:52:23 +08:00
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class ShinTopIO extends TopBase_IO_Bundle{
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2025-08-05 16:49:41 +08:00
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val multiCLK = Input(Vec(16, Bool()))
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2025-04-24 16:18:33 +08:00
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}
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2025-04-02 16:40:25 +08:00
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2025-08-26 10:30:12 +08:00
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class ShinTop extends Module with RequireAsyncReset{
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val io: ShinTopIO = IO(new ShinTopIO)
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2025-04-02 16:40:25 +08:00
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2025-08-26 17:52:23 +08:00
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val mstSlvSwitch = Module(new MstSlvSwitch)
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2025-05-06 17:39:52 +08:00
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val downCDROut = Module(new CDROut)
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val upCDROut = Module(new CDROut)
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2025-09-05 17:15:04 +08:00
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2025-08-26 10:30:12 +08:00
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val downCDRIn = Module(new MPCDRIn)
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val upCDRIn = Module(new MPCDRIn)
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2025-05-06 17:39:52 +08:00
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2025-06-04 16:51:16 +08:00
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2025-08-26 17:52:23 +08:00
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downCDRIn.multiCLK := io.multiCLK
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upCDRIn.multiCLK := io.multiCLK
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2025-06-04 16:51:16 +08:00
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2025-04-27 14:56:07 +08:00
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2025-08-26 17:52:23 +08:00
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downCDROut.io <> mstSlvSwitch.io.downCDROut
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upCDROut.io <> mstSlvSwitch.io.upCDROut
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2025-09-05 17:15:04 +08:00
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2025-08-26 17:52:23 +08:00
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downCDRIn.io <> mstSlvSwitch.io.downCDRIn
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upCDRIn.io <> mstSlvSwitch.io.upCDRIn
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2025-04-27 14:56:07 +08:00
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2025-09-05 17:15:04 +08:00
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2025-08-26 17:52:23 +08:00
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io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
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2025-07-31 15:26:17 +08:00
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2025-08-26 10:30:12 +08:00
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2025-07-31 15:26:17 +08:00
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}
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2025-08-26 10:30:12 +08:00
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