49 lines
881 B
Plaintext
49 lines
881 B
Plaintext
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package BACK
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import chisel3._
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import chisel3.util._
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class AxisNto8IO_Bundle(dw: Int) extends Bundle{
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val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(dw)))
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val deq = Decoupled(new AxisNto8IO_Bundle(8))
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}
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class AxisNto8(dw: Int) extends Module{
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require( dw == 16 | dw == 32 | dw == 64 )
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val io: AxisNto8IO_Bundle = IO(new AxisNto8IO_Bundle(dw))
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val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) )
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val isBusy = RegInit(false.B)
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val fifo = RegEnable( io.enq.bits, io.enq.fire )
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io.enq.ready := ~isBusy | (io.deq.fire & cnt.andR)
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when( io.deq.fire ){
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cnt := cnt + 1.U
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}
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when( io.enq.fire ){
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isBusy := true.B
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} .elsewhen( io.deq.fire & cnt.andR ){
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isBusy := false.B
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}
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io.deq.valid := isBusy
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io.deq.bits.tdata := fifo.tdata >> (cnt << 3)
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io.deq.bits.tlast := fifo.tlast & cnt.andR
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io.deq.bits.tuser := fifo.tuser & cnt.andR
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}
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