eb001/src/main/scala/backBoard/shin/SMUnit.scala

package BACK

import chisel3._
import chisel3.util._


// class SRAM2kWRIO extends Bundle {
//   val addrw = Output(UInt(11.W))
//   val dataw = Output( UInt(8.W) )
//   val enw   = Output(Bool())
// }

// class SRAM2kRDIO extends Bundle {
//   val addrr = Output(UInt(11.W))
//   val datar = Input( UInt(8.W) )
//   val enr   = Output(Bool())
// }

// class SRAM2kIO extends Bundle {
//   val addrr  = Output(UInt(11.W))
//   val addrw  = Output(UInt(11.W))

//   val dataw = Output( UInt(8.W) )
//   val datar = Input( UInt(8.W) )
//   val enw   = Output(Bool())
//   val enr   = Output(Bool())
// }

class SMUnitIO(depth: Int) extends Bundle {

  val sram_w = Flipped(new SRAM2kWRIO)
  val sram_r = Flipped(new SRAM2kRDIO)

  val enq = Input(Bool())
  val deq = Input(Bool())

  val sram = Vec(depth, new SRAM2kIO)

}

abstract class SMUnitBase(depth: Int = 4) extends Module {
  val io: SMUnitIO = IO(new SMUnitIO(depth))
 

  val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
  val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))

  val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
    // ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )


  val isEmpty = ( wPtr === rPtr )


  when( io.enq ){
    wPtr := wPtr + 1.U
  }

  when( io.deq ){
    rPtr := rPtr + 1.U
  }

  for( i <- 0 until depth ){
    io.sram(i).addrw := 0.U
    io.sram(i).dataw := 0.U
    io.sram(i).enw   := false.B

    io.sram(i).addrr := 0.U
    io.sram(i).enr   := false.B
  }

  for( i <- 0 until depth ){
    when( wPtr === i.U & ~isFull ){
      io.sram(i).addrw := io.sram_w.addrw
      io.sram(i).dataw := io.sram_w.dataw
      io.sram(i).enw   := io.sram_w.enw
    }

    when( rPtr === i.U & ~isEmpty){
      io.sram(i).addrr := io.sram_r.addrr
      io.sram(i).enr   := io.sram_r.enr
    }
  }



  io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
    ( rPtr === i.U ) -> io.sram(i).datar,
  })



}

class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {


}