eb001/tb/shinTest/ShinTopTb.v

`timescale 1 ns / 1 ps


module ShinTopTb(

);

    reg clock;
    reg reset;



wire        io_downIn_ready;
reg         io_downIn_valid = 0;
reg  [7:0]  io_downIn_bits_tdata = 0;
reg         io_downIn_bits_tlast = 0;
reg         io_downIn_bits_tuser = 0;

reg         io_downOut_ready = 1;
wire        io_downOut_valid;
wire [7:0]  io_downOut_bits_tdata;
wire        io_downOut_bits_tlast;
wire        io_downOut_bits_tuser;

wire        io_upIn_ready;
reg         io_upIn_valid = 0;
reg  [7:0]  io_upIn_bits_tdata = 0;
reg         io_upIn_bits_tlast = 0;
reg         io_upIn_bits_tuser = 0;

reg         io_upOut_ready = 1;
wire        io_upOut_valid;
wire [7:0]  io_upOut_bits_tdata;
wire        io_upOut_bits_tlast;
wire        io_upOut_bits_tuser;



reg [63:0] timeStamp = 0;








ShinTop s_ShinTop(
  .clock(clock),
  .reset(reset),

  .io_downIn_ready(io_downIn_ready),
  .io_downIn_valid(io_downIn_valid),
  .io_downIn_bits_tdata(io_downIn_bits_tdata),
  .io_downIn_bits_tlast(io_downIn_bits_tlast),
  .io_downIn_bits_tuser(io_downIn_bits_tuser),
  .io_downOut_ready(io_downOut_ready),
  .io_downOut_valid(io_downOut_valid),
  .io_downOut_bits_tdata(io_downOut_bits_tdata),
  .io_downOut_bits_tlast(io_downOut_bits_tlast),
  .io_downOut_bits_tuser(io_downOut_bits_tuser),
  .io_upIn_ready(io_upIn_ready),
  .io_upIn_valid(io_upIn_valid),
  .io_upIn_bits_tdata(io_upIn_bits_tdata),
  .io_upIn_bits_tlast(io_upIn_bits_tlast),
  .io_upIn_bits_tuser(io_upIn_bits_tuser),
  .io_upOut_ready(io_upOut_ready),
  .io_upOut_valid(io_upOut_valid),
  .io_upOut_bits_tdata(io_upOut_bits_tdata),
  .io_upOut_bits_tlast(io_upOut_bits_tlast),
  .io_upOut_bits_tuser(io_upOut_bits_tuser),
  
  .io_timeStamp(timeStamp),

  .io_dSMdeq_0(1'b0),
  .io_dSMdeq_1(1'b0),
  .io_dSMdeq_2(1'b0),
  .io_dSMdeq_3(1'b0),
  .io_uSMenq_0(1'b0),
  .io_uSMenq_1(1'b0),
  .io_uSMenq_2(1'b0),
  .io_uSMenq_3(1'b0),

  .io_sram_w_0_addrw(11'd0),
  .io_sram_w_0_dataw(8'h0),
  .io_sram_w_0_enw(1'b0),
  .io_sram_w_1_addrw(11'd0),
  .io_sram_w_1_dataw(8'h0),
  .io_sram_w_1_enw(1'b0),
  .io_sram_w_2_addrw(11'd0),
  .io_sram_w_2_dataw(8'h0),
  .io_sram_w_2_enw(1'b0),
  .io_sram_w_3_addrw(11'd0),
  .io_sram_w_3_dataw(8'h0),
  .io_sram_w_3_enw(1'b0),
  .io_sram_r_0_addrr(11'd0),
  .io_sram_r_0_datar(),
  .io_sram_r_0_enr(1'b0),
  .io_sram_r_1_addrr(11'd0),
  .io_sram_r_1_datar(),
  .io_sram_r_1_enr(1'b0),
  .io_sram_r_2_addrr(11'd0),
  .io_sram_r_2_datar(),
  .io_sram_r_2_enr(1'b0),
  .io_sram_r_3_addrr(11'd0),
  .io_sram_r_3_datar(),
  .io_sram_r_3_enr(1'b0),

  .io_modeSel(1'b0),

  .io_req_valid(1'b0),
  .io_req_bits_txAddr(15'h0),
  .io_req_bits_rxAddr(15'h0),
  .io_req_bits_length(12'd0),
  .io_rsp_valid(),
  .io_rsp_bits_isError(),
  .io_rsp_bits_length()
);



always @(posedge clock) begin
  timeStamp <= timeStamp + 64'd1;
end







initial begin
	clock = 0;
	reset = 0;

	#100
	reset <= 1;

	#100
	reset <= 0;

#1000000
	$display("Time Out !!!");
	$stop;
end

initial begin
	forever begin #10 clock <= ~clock; end
end

initial
begin
	$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
	$dumpvars(0, ShinTopTb);//tb模块名称
end






















reg [7:0] testDownData[0:1000];

initial begin
  testDownData[0] = 8'hde;
  testDownData[1] = 8'h0e;
end

// reg [11:0] testDownDataCnt = 0;






// always @(posedge clock) begin
  
// end


initial begin
  #1000

  s_ShinTop.slaveParser.localDevIndex = 3; //强制设备索引为3，测试子报文操作

  //主帧头
  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = 8'h20;

  @( io_downIn_valid & io_downIn_ready)

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = 8'h00; //heeader length 512

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = 8'h00;

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = 8'h00;


  //子报文
  for( integer i = 0; i < 8; i = i + 1 ) begin
    if( i != 5 ) begin
      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random; 

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'h0;

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'd56;

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random;

      for( integer j = 0; j < 64-8; j = j+ 1 ) begin
        @(posedge clock) #3 
        io_downIn_valid = 1;
        io_downIn_bits_tdata = 8'ha5; //heeader length 512
      end
    end else begin //第5个子报文操作
      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'h0; 

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'hC; //3号设备 类型空

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'h08; //地址 //SM0

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'h30; //地址 //偏置

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'h30; //命令3 长度56

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = 8'd56; //长度56

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random; //工作计数

      @(posedge clock) #3 
      io_downIn_valid = 1;
      io_downIn_bits_tdata = $random; //工作计数

      for( integer j = 0; j < 64-8; j = j+ 1 ) begin
        @(posedge clock) #3 
        io_downIn_valid = 1;
        io_downIn_bits_tdata = 8'h55; //heeader length 512
      end
    end
  end

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = $random;
  io_downIn_bits_tlast = 0;
  io_downIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = $random;
  io_downIn_bits_tlast = 0;
  io_downIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = $random;
  io_downIn_bits_tlast = 0;
  io_downIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_downIn_valid = 1;
  io_downIn_bits_tdata = $random;
  io_downIn_bits_tlast = 1;
  io_downIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_downIn_valid = 0;
  io_downIn_bits_tlast = 0;




  #1000
  #1000
  #1000
  #1000

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = 8'h20;

  @( io_upIn_valid & io_upIn_ready)

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = 8'h00; //heeader length 512

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = 8'h00; //heeader frameInfo

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = 8'h00; //heeader frameInfo

  for( integer i = 0; i < 8; i = i + 1 ) begin
    if( i != 5 ) begin
      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random; 

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'h0;

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'd56;

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random;

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random;

      for( integer j = 0; j < 64-8; j = j+ 1 ) begin
        @(posedge clock) #3 
        io_upIn_valid = 1;
        io_upIn_bits_tdata = 8'ha5; //heeader length 512
      end
    end else begin //第5个子报文操作
      // io_sram_r_datar = 8'hec;
      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'h0; 

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'hC; //3号设备 类型空

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'h10; //地址SM1

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'h10; //地址偏置

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'h30; //命令3 长度56

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = 8'd56; //长度56

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random; //工作计数

      @(posedge clock) #3 
      io_upIn_valid = 1;
      io_upIn_bits_tdata = $random; //工作计数

      for( integer j = 0; j < 64-8; j = j+ 1 ) begin
        @(posedge clock) #3 
        io_upIn_valid = 1;
        io_upIn_bits_tdata = 8'h55; //heeader length 512
      end
    end
  end

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = $random;
  io_upIn_bits_tlast = 0;
  io_upIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = $random;
  io_upIn_bits_tlast = 0;
  io_upIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = $random;
  io_upIn_bits_tlast = 0;
  io_upIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_upIn_valid = 1;
  io_upIn_bits_tdata = $random;
  io_upIn_bits_tlast = 1;
  io_upIn_bits_tuser = 0;

  @(posedge clock) #3 
  io_upIn_valid = 0;
  io_upIn_bits_tlast = 0;
end




endmodule