121 lines
3.3 KiB
Scala
121 lines
3.3 KiB
Scala
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package Switch
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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class DmaRegIO(implicit p: Parameters) extends SwitchBundle{
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val MacAddr = Output(UInt(48.W))
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val r_TxPtr = Output( Vec(chn, UInt(32.W)) )
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val r_RxPtr = Output( Vec(chn, UInt(32.W)) )
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val r_TxLen = Output( Vec(chn, UInt(16.W)) )
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val r_RxLen = Input ( Vec(chn, UInt(16.W)) )
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val triTx = Output( Vec( chn, Bool()) )
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val triRx = Input ( Vec( chn, Bool()) )
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}
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class DmaReg(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
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// DTS
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val dtsdevice = new SimpleDevice("dma",Seq("dma_0"))
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val configNode = TLRegisterNode(
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address = Seq(AddressSet(0x30001000L, 0x00000fffL)),
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device = dtsdevice,
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concurrency = 1,
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beatBytes = 32/8,
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executable = true
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)
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lazy val module = new DmaRegImp(this)
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}
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class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
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val io: DmaRegIO = IO(new DmaRegIO)
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val txPtr = for( i <- 0 until chn ) yield { RegInit( "h80002000".U(32.W)) }
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val rxPtr = for( i <- 0 until chn ) yield { RegInit( "h80002000".U(32.W)) }
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val txLen = for( i <- 0 until chn ) yield { RegInit( 65535.U(16.W)) }
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// val rxLen = RegInit( 65535.U(16.W))
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val triRx = for( i <- 0 until chn ) yield { RegInit(false.B) }
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for( i <- 0 until chn ) {
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io.r_TxPtr(i) := txPtr(i)
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io.r_RxPtr(i) := rxPtr(i)
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io.r_TxLen(i) := txLen(i)
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}
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for( i <- 0 until chn ) { when( io.triRx(i) ) { triRx(i) := true.B } }
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outer.configNode.regmap(
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( 0 << 2 ) ->
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RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq(
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RegField(32)
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)),
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( 1 << 2 ) ->
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RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq(
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RegField(32)
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)),
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// (0 until chn).map{ i =>
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// ( (10*i + 10) << 2 ) ->
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// RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq(
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// RegField.w(1, RegWriteFn((valid, data) => { io.triTx(i) := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))),
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// RegField(1, triRx(i), RegFieldDesc("bd", s"bd$i", reset=Some(0x0)))
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// ))
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// }
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// (0 until chn).map{ i =>
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// ( (10*i + 11) << 2 ) ->
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// RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq(
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// RegField(16, txLen(i), RegFieldDesc("txLen", "length of tx", reset=Some(65535))),
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// RegField.r(16, io.r_RxLen(i), RegFieldDesc("rxLen", "length of rx")),
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// ))
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// }
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// (0 until chn).map{ i =>
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// ( (10*i + 12) << 2 ) ->
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// RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq(
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// RegField(32, txPtr(i), RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))),
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// ))
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// }
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// (0 until chn).map{ i =>
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// ( (10*i + 13) << 2 ) ->
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// RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq(
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// RegField(32, rxPtr(i), RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))),
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// ))
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// }
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)
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}
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