eb001/src/main/scala/backBoard/shin/SpiInterface.scala

package BACK

import chisel3._
import chisel3.util._

class QSPIInterfaceIO extends Bundle{
  val sck  = Input(Bool())
  val mosi = Input(UInt(4.W))
  val miso = Output(UInt(4.W))
  val isDirIn = Output(Bool())
  val csn  = Input(Bool())
}


class SSPIInterfaceIO extends Bundle{
  val sck  = Input(Bool())
  val mosi = Input(Bool())
  val miso = Output(Bool())
  val csn  = Input(Bool())
}

class RegAccessInterfaceIO extends Bundle{
  val addrSel = Output(UInt(16.W))
  val dataw   = Output( UInt(8.W) )
  val datar   = Input( UInt(8.W) )
  val isEnW   = Output(Bool())
  val isEnR   = Output(Bool())
}

abstract class SpiInterfaceBase extends Module{
  val io = IO(new RegAccessInterfaceIO)

  val sck     = Wire(Bool())
  val csn     = Wire(Bool())


  //数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
  val shiftSCK  = ShiftRegisters(sck, 3, false.B, true.B)
  val shiftCSn  = ShiftRegisters(csn, 3, true.B, true.B)



  val isSckPosedge     = ~shiftSCK(2) & shiftSCK(1)
  val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)


  val exReg = Reg(UInt(8.W))



  val addrSel = Reg(UInt(16.W)); io.addrSel := addrSel
  val spiCmd  = Reg(UInt(8.W))

  val isSpiWrite = spiCmd === 0.U
  val isSpiRead  = spiCmd === 1.U

  val bitSel  = Reg(UInt(3.W))
  val byteSel = Reg(UInt(12.W))


  io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead  & byteSel >= 4.U 
  io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
  io.dataw := exReg

  when( shiftCSn(2) & ~shiftCSn(1) ){
    byteSel  := 0.U
  } .elsewhen( isSckPosedge & ~shiftCSn(1)  ){
    when( bitSel.andR ){
      byteSel := byteSel + 1.U
    }
  }



  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
    addrSel := 0.U
  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
    addrSel := exReg
  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
    addrSel := Cat(exReg, addrSel(7,0))
  } .otherwise{ // byteSel > 1.U
    when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
      addrSel := addrSel + 1.U
    }
  }


  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
    spiCmd  := "hFF".U
  } .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
    spiCmd := exReg
  }




}

class SSpiInterface extends SpiInterfaceBase{
  val spi = IO(new SSPIInterfaceIO)

  sck     := spi.sck
  csn     := spi.csn

  spi.miso := exReg.extract(7)

  when( shiftCSn(2) & ~shiftCSn(1) ){
    bitSel   := 0.U
  } .elsewhen( isSckPosedge & ~shiftCSn(1)  ){
    bitSel := bitSel + 1.U
  }

  val shiftMOSI = ShiftRegisters(spi.mosi, 3)

  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳 //第一个byte
    exReg := 0.U
  } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
    when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
      exReg := 0.U
    } .otherwise{
      when( isSpiWrite ){
        exReg := 0.U
      } .elsewhen( isSpiRead ){
        exReg := io.datar
      } .otherwise{
        assert(false.B, "Assert Failed, empty CMD!\n")
      }
    }
  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
    exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
  }

}

class QSpiInterface extends SpiInterfaceBase{
  val qspi = IO(new QSPIInterfaceIO)

  sck       := qspi.sck
  csn       := qspi.csn
  qspi.miso := exReg(7, 4)
  qspi.isDirIn := isSpiWrite

  when( shiftCSn(2) & ~shiftCSn(1) ){
    bitSel := 0.U
  } .elsewhen( isSckPosedge & ~shiftCSn(1)  ){
    bitSel := ~bitSel
  }

  val shiftMOSI = ShiftRegisters(qspi.mosi, 3)

  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳 //第一个byte
    exReg := 0.U
  } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
    when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
      exReg := 0.U
    } .otherwise{
      when( isSpiWrite ){
        exReg := 0.U
      } .elsewhen( isSpiRead ){
        exReg := io.datar
      } .otherwise{
        assert(false.B, "Assert Failed, empty CMD!\n")
      }
    }
  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
    exReg := Cat( exReg(3,0), shiftMOSI(1) )
  }


}