82 lines
1.4 KiB
Scala
82 lines
1.4 KiB
Scala
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package Switch
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import chisel3._
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import chisel3.util._
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import MAC._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import chisel3.experimental.dataview._
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class SwitchIO(implicit p: Parameters) extends SwitchBundle{
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val mii = Vec( chn, new MII )
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val isLoopBack = Output(Vec( chn, Bool()))
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val asyncReset = Input(AsyncReset())
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}
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class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
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val ethReg = LazyModule(new MacReg)
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lazy val module = new SwitchImp(this)
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}
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class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
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val io = IO(new SwitchIO)
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val mac = ( 0 until chn ).map{ i =>
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Module(new Mac)
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}
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( 0 until chn ).map{ i =>
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mac(i).io.mii <> io.mii(i)
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mac(i).io.asyncReset := io.asyncReset
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io.isLoopBack(i) := mac(i).io.isLoopBack
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}
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outer.ethReg.module.io.asyncReset := io.asyncReset
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outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
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val rxBuff = Module(new RxBuff)
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rxBuff.io.enq <> mac(0).io.rxEnq
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rxBuff.io.deq.data.ready := false.B
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rxBuff.io.deq.ctrl.ready := false.B
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val txBuff = Module(new TxBuff)
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txBuff.io.deq <> mac(0).io.txDeq
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txBuff.io.enq.ctrl.valid := false.B
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txBuff.io.enq.data.valid := false.B
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txBuff.io.enq.data.bits := 0.U
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}
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