101 lines
2.0 KiB
Scala
101 lines
2.0 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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class MirrorSRAMIO extends Bundle{
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val datar_a = Output(UInt(8.W))
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val datar_b = Output(UInt(8.W))
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val clk_a = Input(Bool())
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val clk_b = Input(Bool())
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val reset_a = Input(Bool())
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val reset_b = Input(Bool())
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val ce_a = Input(Bool())
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val ce_b = Input(Bool())
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val we_a = Input(Bool())
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val we_b = Input(Bool())
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val addr_a = Input(UInt(11.W))
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val addr_b = Input(UInt(11.W))
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val dataw_a = Input(UInt(8.W))
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val dataw_b = Input(UInt(8.W))
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}
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class MirrorSRAM extends BlackBox with HasBlackBoxInline {
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val io: MirrorSRAM = IO(new MirrorSRAM)
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setInline("lvds_bus_master.v",
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"""
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| module MirrorSRAM(
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| output [7:0] datar_a,
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| output [7:0] datar_b,
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| input clock,
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| input reset,
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| input ce_a,
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| input ce_b,
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| input we_a,
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| input we_b,
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| input [10:0] addr_a,
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| input [10:0] addr_b,
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| input [7:0] dataw_a
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| input [7:0] dataw_b
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| );
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| wire [15:0] doa;
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| wire [15:0] dob;
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| assign datar_a = doa[7:0];
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| assign datar_b = dob[7:0];
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| DPB bram_dpb_0 (
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| .DOA(doa),
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| .DOB(dob),
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| .CLKA(clock),
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| .OCEA(1'b1),
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| .CEA(ce_a),
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| .RESETA(reset),
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| .WREA(we_a),
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| .CLKB(clock),
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| .OCEB(1'b1),
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| .CEB(ce_b),
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| .RESETB(reset),
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| .WREB( we_b ),
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| .BLKSELA(3'b0),
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| .BLKSELB(3'b0),
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| .ADA({addr_a[10:0],3'b000}),
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| .DIA({8'b0,dataw_a}),
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| .ADB({addr_b[10:0],3'b000}),
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| .DIB({8'b0,dataw_b})
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| );
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| defparam bram_dpb_0.READ_MODE0 = 1'b0;
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| defparam bram_dpb_0.READ_MODE1 = 1'b0;
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| defparam bram_dpb_0.WRITE_MODE0 = 2'b00;
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| defparam bram_dpb_0.WRITE_MODE1 = 2'b00;
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| defparam bram_dpb_0.BIT_WIDTH_0 = 8;
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| defparam bram_dpb_0.BIT_WIDTH_1 = 8;
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| defparam bram_dpb_0.RESET_MODE = "SYNC";
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| );
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|endmodule
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""".stripMargin)
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}
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