eb001/src/main/scala/backBoard/ebus/CDRIn.scala

package BACK

import chisel3._
import chisel3.util._


//work in 100MHZ
class CDRInIO extends Bundle{
  val axis = Decoupled(new AXIS_Bundle(8))
  val serDat = Input(Bool())
  val flush = Input(Bool())
}


abstract class CDRInBase extends Module with RequireAsyncReset{


  val io: CDRInIO = IO(new CDRInIO)


  val syncSerDat = Wire(Bool())
}


trait CDRInMultiSample{ this: CDRInBase =>
  
  val clkNum: Int = 16
  require( clkNum == 16 )


  //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
  val multiCLK = IO(Input(Vec(clkNum, Bool())))



  val sampleReg = Wire(Vec(clkNum, Bool()))
  
  for( i <- 0 until clkNum ) {
    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
  }

  val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))



  for( i <- 0 until clkNum ){
    sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
  }

  for( i <- clkNum until 2*clkNum ){
    sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
  }

  /*
  val flitReg =
    for( i <- 1 until 22 ) yield {
      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
    }

  val asyncSerDat = PopCount(flitReg) >= 11.U
  */

  val flitReg =
    for( i <- 1 until (2*clkNum)-1 ) yield {
      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
    }

  val clearCnt = Reg(UInt(4.W))
  val checkCnt = Reg(UInt(4.W))
  val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W ))
  val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
  val isLock = RegInit(false.B)

  when( sampleReg_sync.reduce(_|_) === false.B ){
    when( clearCnt =/= 10.U ){
      clearCnt := clearCnt + 1.U
    }
  } .otherwise{
    clearCnt := 0.U
  }

  when( ~isLock ){
    checkCnt := 0.U
  } .otherwise{
    checkCnt := checkCnt + 1.U
  }

  //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的

      when( ~isLock ){
        for( i <- 3 until 19 ){
          val j = 19 - i - 1
          when( flitReg(j) ^ flitReg(j+1) ){
            arbLock := j.U
            arbCali := j.U
          }
        }
      }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
        for( i <- 0 until 22 ){
          val j = 22 - i -1
          when( flitReg(j) ^ flitReg(j+1) ){
            when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
              arbCali := arbCali - 1.U
            } .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
              arbCali := arbCali + 1.U
            }
          }
        }
      }

  when( io.flush ){
    isLock := false.B
  } .elsewhen( ~isLock ){
    for( i <- 3 until 19 ){
      val j = 19 - i - 1
      when( flitReg(j) ^ flitReg(j+1) ){
        isLock := true.B
      }
    }
  } .elsewhen( clearCnt === 10.U ){
    isLock := false.B
  }


  val asyncSerDat = 
    Mux1H(
      (for { i <- 0 until 22 } yield {
        (arbCali === i.U) -> flitReg(i+(8))
      })
    )


  syncSerDat := asyncSerDat

}



trait CDRInAxis{ this: CDRInBase =>

  def HeaderByte: Int = 4

  val ETH_PRE = "b1100010001".U(10.W)
  val ETH_SFD = "b0110100111".U(10.W)

  val STATE_IDLE = 0.U
  val STATE_HEADER = 1.U
  val STATE_PAYLOAD = 2.U

  val stateNext = Wire(UInt(2.W))
  val stateCurr = RegNext( stateNext, STATE_IDLE )

  val bitCnt = Reg(UInt(4.W))
  val byteCnt = RegInit(0.U((12+1).W))

  val checkSFD = RegInit( 0.U(20.W) )

  when( io.flush ){
    checkSFD := 0.U
  } .otherwise{
    checkSFD := Cat( checkSFD(18,0), syncSerDat )
  }

  val shiftData = Dualb4b5Decoder(checkSFD(9,0))

  val payloadLen = RegInit(0.U(12.W))

  when( io.flush ){
    payloadLen := 0.U
  } .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
    payloadLen := Cat( shiftData, 0.U(4.W) )
  } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
  }
  
  stateNext := 
    Mux( io.flush, STATE_IDLE,
      Mux1H(Seq(
        (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
        (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
        (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U)  ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD  )), // PAYLOAD
      ))                                                                  //crc
    )





  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
    bitCnt := 0.U
  } .otherwise{
    when( bitCnt === 9.U ){
      bitCnt := 0.U
    } .otherwise{
      bitCnt := bitCnt + 1.U
    }
  }

  when( io.flush ){
    byteCnt := 0.U
  } .elsewhen( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
    byteCnt := 0.U
  } .elsewhen( bitCnt === 9.U ){
    when( stateCurr === STATE_HEADER ){
      byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
      assert( byteCnt <= (HeaderByte-1).U )
    } .elsewhen( stateCurr === STATE_PAYLOAD ){
      byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
      assert( byteCnt <= ( payloadLen+ (4-1).U ) )
    }
  }





  val axis_valid = RegInit(false.B)
  val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
  val axis_tuser = false.B
  val axis_tlast = RegInit( false.B )



  io.axis.valid := axis_valid
  io.axis.bits.tdata := axis_tdata
  io.axis.bits.tuser := axis_tuser
  io.axis.bits.tlast := axis_tlast

  when( io.flush ){
    axis_valid := false.B
  } .elsewhen( io.axis.fire ){
    axis_valid := false.B
  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
    axis_valid := true.B
  }

  when( io.flush ){
    axis_tlast := false.B
  } .otherwise{
    axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE)
  }

}

class MPCDRIn extends CDRInBase 
with CDRInAxis
with CDRInMultiSample