79 lines
2.1 KiB
Scala
79 lines
2.1 KiB
Scala
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package MAC
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import chisel3._
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import chisel3.util._
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class TxBuffDesc extends Bundle{
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val len = UInt(16.W) //[31.16]
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val rd = Bool() //[15]
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val irq = Bool() //14
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val wr = Bool() //13
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val pad = Bool() //12
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val crc = Bool() //11
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val reserved1 = UInt(2.W) //10,9
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val ur = Bool() //8
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val rtry = UInt(4.W) //7 6 5 4
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val rl = Bool() //3
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val lc = Bool() //2
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val df = Bool() //1
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val cs = Bool() //0
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}
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class RxBuffDesc extends Bundle{
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val len = UInt(16.W) //[31.16]
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val e = Bool() //15
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val irq = Bool() //14
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val wrap = Bool() //13
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val reserved1 = UInt(4.W) //12 11 10 9
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val cf = Bool() //8
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val m = Bool() //7
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val or = Bool() //6
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val is = Bool() //5
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val dn = Bool() //4
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val tl = Bool() //3
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val sf = Bool() //2
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val crc = Bool() //1
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val lc = Bool() //0
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}
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trait MacWishboneMasterIO{ this: Bundle =>
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val m_wb_adr_o = Output(UInt(32.W))
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val m_wb_sel_o = Output(UInt(4.W))
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val m_wb_we_o = Output(Bool())
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val m_wb_dat_i = Input(UInt(32.W))
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val m_wb_dat_o = Output(UInt(32.W))
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val m_wb_cyc_o = Output(Bool())
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val m_wb_stb_o = Output(Bool())
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val m_wb_ack_i = Input(Bool())
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val m_wb_err_i = Input(Bool())
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val m_wb_cti_o = Output(UInt(3.W))
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val m_wb_bte_o = Output(UInt(2.W))
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}
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trait MacWishboneSlaveIO{ this: Bundle =>
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val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input
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val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output
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val WB_ADR_I = Input(UInt(12.W)) // WISHBONE address input
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val WB_WE_I = Input(Bool()) // WISHBONE write enable input
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val WB_SEL_I = Input(UInt(4.W)) // WISHBONE byte select input
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val WB_CYC_I = Input(Bool()) // WISHBONE cycle input
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val WB_STB_I = Input(Bool()) // WISHBONE strobe input
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val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output
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val WB_ERR_O = Output(Bool()) // WISHBONE error output
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}
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trait MDIO { this: Bundle =>
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val mdi = Input( Bool()) // MII Management Data In
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val mdc = Output(Bool()) // MII Management Data Clock
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val mdo = Output(Bool()) // MII Management Data Output
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val mdoEn = Output(Bool()) // MII Management Data Output Enable
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}
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