85 lines
1.8 KiB
Scala
85 lines
1.8 KiB
Scala
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package MAC
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.devices.tilelink._
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class MacAXI(implicit p: Parameters) extends Mac{
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val memAXI4SlaveNode = AXI4SlaveNode(Seq(
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AXI4SlavePortParameters(
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slaves = Seq(
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AXI4SlaveParameters(
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address = Seq(AddressSet(0x00000000L, 0x7fffffffL)),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsRead = TransferSizes(32/8, 32/8),
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supportsWrite = TransferSizes(32/8, 32/8)
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)
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),
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beatBytes = 32 / 8
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)
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))
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memAXI4SlaveNode :=
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AXI4UserYanker() :=
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AXI4IdIndexer(1) :=
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AXI4Deinterleaver(32/8) :=
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TLToAXI4() :=
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TLWidthWidget(32 / 8) :=
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tlClientNode
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val axiConfigPort =
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AXI4MasterNode(
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Seq(AXI4MasterPortParameters(
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Seq(AXI4MasterParameters(
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name = "Mac Config",
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id = IdRange(0, 1),
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maxFlight = Some(1),
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))
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))
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)
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val tlError = LazyModule(new TLError(
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params = DevNullParams(
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address = Seq(AddressSet(0x0, 0x2fffffffL)),
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maxAtomic = 0,
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maxTransfer = 32/8),
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beatBytes = 32 / 8
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))
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val xbar = TLXbar()
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tlMasterNode := xbar := TLFIFOFixer() := TLWidthWidget(32/8) := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := AXI4Buffer() := AXI4IdIndexer(1) := axiConfigPort
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tlError.node := xbar
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val intSinkNode = IntSinkNode(IntSinkPortSimple())
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intSinkNode := int_node
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val axiCfg = InModuleBody {
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axiConfigPort.makeIOs()
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}
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val axiMem = InModuleBody {
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memAXI4SlaveNode.makeIOs()
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}
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val int = InModuleBody {
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intSinkNode.makeIOs()
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}
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}
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