eb001/src/main/scala/backBoard/shin/MasterParser.scala

package BACK

import chisel3._
import chisel3.util._

class MasterParserIO extends Module{
  val downOut = Decoupled(new AXIS_Bundle(8))
  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )

  val sram_r = Flipped(new ShareSRAMIO)
  val sram_w = Flipped(new ShareSRAMIO)

  val req = Valid(new Bundle{
    val txAddr    = UInt(15.W)
    val rxAddr    = UInt(15.W)
    val length  = UInt(12.W)
  })
  val rsp = Valid(new Bundle{
    val isError = Bool()
    val length  = UInt(12.W)
  })

  val rxEnq = Output( Bool())
  val txDeq  = Output( Bool())

  val trigAddr = Input( Vec(2, UInt(15.W)) )

  val timeStamp = Input(UInt(64.W))

}

abstract class MasterParserBase extends Module{
  val io: MasterParserIO = IO(new MasterParserIO)

  val sendCnt = Reg(UInt(11.W))
  val sendLen = Reg(UInt(11.W))
  val txAddr = Reg(UInt(15.W))

  val rxCnt = Reg(UInt(11.W))
  val rxAddr = Reg(UInt(15.W))

  val reqReady = RegInit(true.B)
  val sendAddr = Reg(UInt(12.W))

  io.req.ready := reqReady

  when( io.req.fire ){
    reqReady := false.B
  } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
    reqReady := true.B
  }

  when( io.req.fire ){
    sendLen  := io.req.bits.length
    sendCnt  := 0.U
  } .elsewhen( io.downOut.fire ){
    sendCnt := sendCnt + 1.U
  }

  when( io.req.fire ){
    txAddr := io.req.bits.txAddr
  } .elsewhen( io.downOut.fire ){
    txAddr := txAddr + 1.U
  }

  when( io.req.fire ){
    rxAddr := io.req.bits.rxAddr
  } .elsewhen( io.upIn.fire ){
    rxAddr := rxAddr + 1.U
  }

  when( reqReady ){
    sendAddr := 0.U
  } .elsewhen( io.downOut.fire ){
    sendAddr := sendAddr + 1.U
  }

  io.sram_r.enr := 
    io.req.fire | io.downOut.fire

  io.sram_r.addr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )

  io.downOut.valid := ~reqReady
  io.downOut.bits.tdata := io.sram_r.datar
  io.downOut.bits.tuser := false.B 
  io.downOut.bits.tlast := sendCnt === sendLen





  when( io.req.fire ){
    rxCnt := 0.U
  } .elsewhen( io.upIn.fire ){
    rxCnt := rxCnt + 1.U
  }


  io.upIn.ready := true.B

  io.sram_w.enw := io.upIn.fire
  io.sram_w.addr := rxAddr
  io.sram_w.dataw := io.upIn.bits.tdata


  io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
  io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
  io.rsp.bits.length  := rxCnt + 1.U



  io.rxEnq := io.trigAddr(0) === txCnt         & io.downOut.fire
  io.txDeq := io.trigAddr(1) === (rxCnt + 1.U) & io.upIn.fire



}


class MasterParser extends MasterParserBase{

}