2025-02-10 14:38:49 +08:00
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#include "system_cfg.h"
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#include "sysDef.h"
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#include "tl2cdr.h"
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#include "halfLvdsMacSvr.h"
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2025-02-10 23:59:35 +08:00
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#include "plic.h"
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2025-02-10 14:38:49 +08:00
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//-------------------------------------------------------------------
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uint8_t MST_TX_BUF[TX_BUF_NUM * TX_BUF_MAX_LEN] __attribute__((aligned(32)));
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uint8_t MST_RX_BUF[RX_BUF_NUM * RX_BUF_MAX_LEN] __attribute__((aligned(32)));
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//-------------------------------------------------------------------
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extern const uint8_t int_svr_code[];
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uint32_t (*sys_call)(uint32_t no, ...);
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/*
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#define CDR_INT_TX0END 14U
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#define CDR_INT_TX1END 15U
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#define CDR_INT_RX0ERROR 16U
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#define CDR_INT_RX1ERROR 17U
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#define CDR_INT_RX0START 18U
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#define CDR_INT_RX1START 19U
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#define CDR_INT_RX0END 20U
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#define CDR_INT_RX1END 21U
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#define CDR_INT_TX0_FIFO_DEQ 22U
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#define CDR_INT_TX1_FIFO_DEQ 23U
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#define CDR_INT_RX0_FIFO_ENQ 24U
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#define CDR_INT_RX1_FIFO_ENQ 25U
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*/
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volatile uint32_t isr_flag[32] = {0};
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uint32_t HLM_poll(uint32_t mode)
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{
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2025-02-12 15:58:50 +08:00
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sys_call = (void *)int_svr_code;
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//复位脉冲
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*tx0_softReset = 1;
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*tx1_softReset = 1;
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*rx0_softReset = 1;
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*rx1_softReset = 1;
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2025-02-10 14:38:49 +08:00
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if (mode == WORKMODE_MASTER)
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{
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2025-02-12 01:17:54 +08:00
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uint32_t tx_pkt_len = 256;
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2025-02-10 23:59:35 +08:00
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uint32_t rx_pkt_len = 0;
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uint32_t rx_start = 0;
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uint32_t status;
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2025-02-10 14:38:49 +08:00
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uint32_t i;
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2025-02-10 23:59:35 +08:00
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uint32_t *tx_data_ptr = (uint32_t *)MST_TX_BUF;
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uint32_t *rx_data_ptr = (uint32_t *)MST_RX_BUF;
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2025-02-10 14:38:49 +08:00
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//准备数据
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2025-02-10 23:59:35 +08:00
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for (i = 0; i < tx_pkt_len; i++)
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2025-02-10 14:38:49 +08:00
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MST_TX_BUF[i] = i;
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//开始发送工作
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2025-02-11 17:56:44 +08:00
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*tx0_txLen = tx_pkt_len + 4;
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2025-02-12 01:17:54 +08:00
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*tx0_txFifo = (tx_pkt_len << 20) | 0;
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2025-02-10 14:38:49 +08:00
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uint32_t tx_index = 0;
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uint32_t rx_index = 0;
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2025-02-10 23:59:35 +08:00
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for (i = 0; i < HLM_TX_FIFO_LEN - 1; i++)
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{
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if ((tx_index * 4) < tx_pkt_len)
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{
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*tx0_txFifo = tx_data_ptr[tx_index];
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tx_index++;
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}
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else
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break;
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}
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2025-02-10 14:38:49 +08:00
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while (1)
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{
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2025-02-10 23:59:35 +08:00
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status = *HLM_status;
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2025-02-11 17:56:44 +08:00
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if (((tx_index * 4) < tx_pkt_len) && (!(status & HLM_TX0_FIFO_FULL)))
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2025-02-10 14:38:49 +08:00
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{
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2025-02-10 23:59:35 +08:00
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*tx0_txFifo = tx_data_ptr[tx_index];
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tx_index++;
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}
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2025-02-12 01:17:54 +08:00
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status = *HLM_status;
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if (((tx_index * 4) < tx_pkt_len) && (!(status & HLM_TX0_FIFO_FULL)))
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{
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*tx0_txFifo = tx_data_ptr[tx_index];
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tx_index++;
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}
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2025-02-10 23:59:35 +08:00
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if ((rx_start) && (status & HLM_RX1_VALID))
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{
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rx_data_ptr[rx_index] = *rx1_rxFifo;
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if (rx_index == 0)
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rx_pkt_len = (rx_data_ptr[rx_index] >> 20) + 4;
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rx_index++;
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if (rx_pkt_len <= (rx_index * 4))
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2025-02-10 14:38:49 +08:00
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{
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2025-02-10 23:59:35 +08:00
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rx_start = 0;
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2025-02-12 01:17:54 +08:00
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rx_index = 0;
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break;
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2025-02-10 14:38:49 +08:00
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}
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}
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if (isr_flag[CDR_INT_RX1START])
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{
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isr_flag[CDR_INT_RX1START] = 0;
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2025-02-10 23:59:35 +08:00
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rx_start = 1;
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rx_index = 0;
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2025-02-10 14:38:49 +08:00
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}
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}
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}
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else if (mode == WORKMODE_SLAVE)
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{
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uint32_t rx_index = 0;
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2025-02-10 23:59:35 +08:00
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uint32_t tx_pkt_len;
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uint32_t rx_pkt_len = 0;
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uint32_t rx_start = 0;
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uint32_t status;
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2025-02-12 01:17:54 +08:00
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*rx0_rxTxPair = 1;
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*rx0_rxTimerAim = 0; //240;
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*rx1_rxTxPair = 0;
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*rx1_rxTimerAim = 0;
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*plic_enable_0_31 = 0;
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2025-02-12 15:58:50 +08:00
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#ifdef __riscv_e
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sys_call(SYS_SLAVE_WORK);
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2025-02-12 01:17:54 +08:00
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2025-02-12 15:58:50 +08:00
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#else
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while(1)
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{
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status = *HLM_status;
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if (status & HLM_RX0_VALID)
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{
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rx_start = 1;
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break;
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}
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}
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2025-02-10 23:59:35 +08:00
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2025-02-10 14:38:49 +08:00
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while (1)
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{
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2025-02-11 17:56:44 +08:00
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status = *HLM_status;
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2025-02-10 14:38:49 +08:00
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2025-02-11 17:56:44 +08:00
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if (rx_start && (status & HLM_RX0_VALID))
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2025-02-10 14:38:49 +08:00
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{
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2025-02-10 23:59:35 +08:00
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uint32_t data;
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data = *rx0_rxFifo;
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if (rx_index == 0)
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{
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rx_pkt_len = (data >> 20) + 4;
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2025-02-11 17:56:44 +08:00
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*tx1_txLen = rx_pkt_len;
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2025-02-10 23:59:35 +08:00
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}
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2025-02-10 14:38:49 +08:00
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2025-02-10 23:59:35 +08:00
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rx_index++;
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*tx1_txFifo = data;
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if (rx_pkt_len <= (rx_index * 4))
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{
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rx_start = 0;
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2025-02-12 15:58:50 +08:00
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break;
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2025-02-10 23:59:35 +08:00
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}
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}
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2025-02-10 14:38:49 +08:00
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}
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2025-02-12 15:58:50 +08:00
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#endif
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2025-02-10 14:38:49 +08:00
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}
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else
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{
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}
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}
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