52 lines
953 B
Scala
52 lines
953 B
Scala
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package MAC
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
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val mac = LazyModule( new Mac )
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val tlRAM = TLRAM(
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address = AddressSet(0x00000000L, 0x001FFFFFL),
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cacheable = false,
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executable = false,
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atomics = false,
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beatBytes = 4,
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sramReg = true,
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devName = None,
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)
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tlRAM := mac.tlClientNode
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if( !isTileLink ){} else {
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val tlClientIONode =
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TLClientNode(Seq(TLMasterPortParameters.v1(
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Seq(TLMasterParameters.v1(
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name = "tlSlvIO",
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sourceId = IdRange(0, 1),
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))
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)))
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mac.tlMasterNode.get := tlClientIONode
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val tlSlv = InModuleBody {
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tlClientIONode.makeIOs()
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}
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}
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new MacIO with MDIO)
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io <> mac.module.io
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}
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}
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