eb001/src/main/scala/backBoard/shin/MstSlvSwitch.scala

package BACK

import chisel3._
import chisel3.util._

class TopBase_IO_Bundle extends Bundle{
  val dDatIn   = Input(Bool())
  val dDatOut  = Output(Bool())
  val uDatIn   = Input(Bool())
  val uDatOut  = Output(Bool())

  val iqspi = new QSPIInterfaceIO
  val ospi = new SSPIInterfaceIO
  val oqspi = new QSPIInterfaceIO

  val iSync = Output(Vec(4, Bool()))

  val isSoftReset = Output(Bool())

  val interrupt = Output(Bool())

  val latchPin = Input(Vec(2, Bool()))
  val hwSerial = Input(UInt(48.W))
  val uniCode = Input(UInt(64.W))

  val pllCtrl = Output(UInt(32.W))
  val xtal    = Output(UInt(12.W))
  val anamuxSel = Output(UInt(5.W))
  val ldo2p5 = Output(UInt(8.W))
  val ldo1p1 = Output(UInt(8.W))
  val refTop = Output(UInt(3.W))
  val bias   = Output(UInt(2.W))

  val spiSel  = Output(UInt(2.W))
  val isPllCfg = Output(Bool())
}



class MstSlvSwitchIO extends TopBase_IO_Bundle{
  val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
  val upCDRSampleIn   = Vec(3, Flipped(new CDRInSampleIO) )
}






abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{

  val io: MstSlvSwitchIO = IO(new MstSlvSwitchIO)

  val downCDROut = Module(new CDROut)
  val upCDROut   = Module(new CDROut)

  val downCDRInAxis = Module(new CDRInAxis)
  val upCDRInAxis = Module(new CDRInAxis)

  val slaveParser  = Module(new SlaveParser )
  val masterParser = Module(new MasterParser)

  val b4b5DownEncoder = Module(new b4b5DualEncode)
  val b4b5DownDecoder = Module(new b4b5DualDecode)
  val b4b5UpEncoder = Module(new b4b5DualEncode)
  val b4b5UpDecoder = Module(new b4b5DualDecode)

  val b8b10DownEncoder = Module(new b8b10Encode)
  val b8b10DownDecoder = Module(new b8b10Decode)
  val b8b10UpEncoder = Module(new b8b10Encode)
  val b8b10UpDecoder = Module(new b8b10Decode)

  val interface = Module(new Interface)

  val downInSerDat = Wire(Bool())
  val downInSyncSerDat = Wire(Bool()); downCDRInAxis.io.syncSerDat := downInSyncSerDat
  val upInSerDat = Wire(Bool())
  val upInSyncSerDat = Wire(Bool()); upCDRInAxis.io.syncSerDat := upInSyncSerDat

  dontTouch(downInSerDat)
  dontTouch(downInSyncSerDat)
  dontTouch(upInSerDat)
  dontTouch(upInSyncSerDat)

  interface.io.latchPin  := io.latchPin
  interface.io.uniCode   := io.uniCode
  interface.io.hwSerial  := io.hwSerial

  interface.io.intTransEnd(0) := downCDRInAxis.io.axis.fire  & downCDRInAxis.io.axis.bits.tlast
  interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast
  interface.io.intTransEnd(2) := upCDRInAxis.io.axis.fire    & upCDRInAxis.io.axis.bits.tlast
  interface.io.intTransEnd(3) := upCDROut.io.axis.fire   & upCDROut.io.axis.bits.tlast
  
  io.isSoftReset := interface.io.isSoftReset
  io.interrupt   := interface.io.interrupt

  io.ospi  <> interface.io.ospi
  io.iqspi <> interface.io.iqspi
  io.oqspi <> interface.io.oqspi

  io.iSync := interface.io.sync


  io.pllCtrl := interface.io.cReg.pllCtrl
  io.xtal    := interface.io.cReg.xtal
  io.anamuxSel := interface.io.cReg.anamuxSel
  io.ldo2p5    := interface.io.cReg.ldo2p5
  io.ldo1p1    := interface.io.cReg.ldo1p1
  io.refTop    := interface.io.cReg.refTop
  io.bias      := interface.io.cReg.bias

  io.spiSel   := interface.io.cReg.spiSel
  io.isPllCfg := interface.io.isPllCfg

  val sram = Seq(
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
  )


  val smUnit = Seq(
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
  )

  val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
  val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
  val lvdsSMComf = for( i <- 0 until 4 ) yield WireDefault(false.B)
  val lvdsSMAbrt = for( i <- 0 until 4 ) yield WireDefault(false.B)

  smUnit(0).io.enq := lvdsSMEnq(0)
  smUnit(2).io.enq := lvdsSMEnq(1)
  smUnit(4).io.enq := lvdsSMEnq(2)
  smUnit(6).io.enq := lvdsSMEnq(3)

  smUnit(0).io.isComf := lvdsSMComf(0)
  smUnit(2).io.isComf := lvdsSMComf(1)
  smUnit(4).io.isComf := lvdsSMComf(2)
  smUnit(6).io.isComf := lvdsSMComf(3)

  smUnit(0).io.isAbrt := lvdsSMAbrt(0)
  smUnit(2).io.isAbrt := lvdsSMAbrt(1)
  smUnit(4).io.isAbrt := lvdsSMAbrt(2)
  smUnit(6).io.isAbrt := lvdsSMAbrt(3)

  smUnit(1).io.deq := lvdsSMDeq(0)
  smUnit(3).io.deq := lvdsSMDeq(1)
  smUnit(5).io.deq := lvdsSMDeq(2)
  smUnit(7).io.deq := lvdsSMDeq(3)

  smUnit(0).io.sram_r <> interface.io.sram_r(0)
  smUnit(2).io.sram_r <> interface.io.sram_r(1)
  smUnit(4).io.sram_r <> interface.io.sram_r(2)
  smUnit(6).io.sram_r <> interface.io.sram_r(3)

  smUnit(1).io.sram_w := interface.io.sram_w(0)
  smUnit(3).io.sram_w := interface.io.sram_w(1)
  smUnit(5).io.sram_w := interface.io.sram_w(2)
  smUnit(7).io.sram_w := interface.io.sram_w(3)

  smUnit(0).io.deq := interface.io.dSMdeq(0)
  smUnit(2).io.deq := interface.io.dSMdeq(1)
  smUnit(4).io.deq := interface.io.dSMdeq(2)
  smUnit(6).io.deq := interface.io.dSMdeq(3)


  smUnit(1).io.enq := interface.io.uSMenq(0)
  smUnit(3).io.enq := interface.io.uSMenq(1)
  smUnit(5).io.enq := interface.io.uSMenq(2)
  smUnit(7).io.enq := interface.io.uSMenq(3)

  smUnit(1).io.isComf := RegNext( smUnit(1).io.enq, false.B )
  smUnit(3).io.isComf := RegNext( smUnit(3).io.enq, false.B )
  smUnit(5).io.isComf := RegNext( smUnit(5).io.enq, false.B )
  smUnit(7).io.isComf := RegNext( smUnit(7).io.enq, false.B )

  smUnit(1).io.isAbrt := false.B
  smUnit(3).io.isAbrt := false.B
  smUnit(5).io.isAbrt := false.B
  smUnit(7).io.isAbrt := false.B

  for( i <- 0 until 8 ){
    interface.io.smUsedDepth(i) := smUnit(i).io.cnt
    smUnit(i).io.flush := interface.io.isSMReset(i)
  }


  for( i <- 0 until 4 ){
    for( j <- 0 until 4 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }
  }

  for( i <- 4 until 8 ){
    for( j <- 0 until 2 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }    
  }




  //default
  {
    smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)

    smUnit(1).io.sram_r.enr := false.B
    smUnit(3).io.sram_r.enr := false.B
    smUnit(5).io.sram_r.enr := false.B
    smUnit(7).io.sram_r.enr := false.B
    smUnit(1).io.sram_r.addrr := 0.U
    smUnit(3).io.sram_r.addrr := 0.U
    smUnit(5).io.sram_r.addrr := 0.U
    smUnit(7).io.sram_r.addrr := 0.U

    slaveParser.io.sram_r(0).datar := 0.U
    slaveParser.io.sram_r(1).datar := 0.U
    slaveParser.io.sram_r(2).datar := 0.U
    slaveParser.io.sram_r(3).datar := 0.U
    masterParser.io.sram_r.datar := 0.U

    downCDRInAxis.io.axis.ready := false.B
    slaveParser.io.downIn.valid := false.B
    slaveParser.io.downIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.downOut.ready := false.B
    masterParser.io.downOut.ready := false.B
    downCDROut.io.axis.valid := false.B
    downCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    upCDRInAxis.io.axis.ready := false.B
    slaveParser.io.upIn.valid := false.B
    slaveParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
    masterParser.io.upIn.valid := false.B
    masterParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.upOut.ready := false.B
    upCDROut.io.axis.valid := false.B
    upCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    interface.io.mstDeltaTime := 0.U

    interface.io.slvDeltaTime := 0.U
    interface.io.deltaFinal   := 0.U

    interface.io.intMstTrig(0) := false.B
    interface.io.intMstTrig(1) := false.B

    interface.io.intSlvTrig(0) := false.B
    interface.io.intSlvTrig(1) := false.B
    interface.io.intSlvTrig(2) := false.B
    interface.io.intSlvTrig(3) := false.B
    interface.io.intSlvTrig(4) := false.B
    interface.io.intSlvTrig(5) := false.B
    interface.io.intSlvTrig(6) := false.B
    interface.io.intSlvTrig(7) := false.B

    interface.io.intHWTrig(0) := false.B
    interface.io.intHWTrig(1) := false.B

    interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
    interface.io.upRecStat   := 0.U.asTypeOf(new Stat_IO_Bundle)
  }

}

trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>

  when( interface.io.cReg.modeSel === true.B ){
    masterParser.io.downOut <> downCDROut.io.axis
    masterParser.io.upIn    <> upCDRInAxis.io.axis
  }

  when( interface.io.cReg.modeSel === true.B ){

    when( interface.io.txReq.bits.rxSM === 0.U ){
      smUnit(0).io.sram_w := masterParser.io.sram_w
      lvdsSMEnq(0)  := masterParser.io.rxEnq
      lvdsSMComf(0) := RegNext(masterParser.io.rxEnq, false.B)
      lvdsSMAbrt(0) := false.B
    } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
      smUnit(2).io.sram_w := masterParser.io.sram_w
      lvdsSMEnq(1)  := masterParser.io.rxEnq
      lvdsSMComf(1) := RegNext(masterParser.io.rxEnq, false.B)
      lvdsSMAbrt(1) := false.B
    } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
      smUnit(4).io.sram_w := masterParser.io.sram_w
      lvdsSMEnq(2)  := masterParser.io.rxEnq
      lvdsSMComf(2) := RegNext(masterParser.io.rxEnq, false.B)
      lvdsSMAbrt(2) := false.B
    } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
      smUnit(6).io.sram_w := masterParser.io.sram_w
      lvdsSMEnq(3)  := masterParser.io.rxEnq
      lvdsSMComf(3) := RegNext(masterParser.io.rxEnq, false.B)
      lvdsSMAbrt(3) := false.B
    }

    when( interface.io.txReq.bits.txSM === 0.U ){
      smUnit(1).io.sram_r <> masterParser.io.sram_r
      lvdsSMDeq(0)    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
      smUnit(3).io.sram_r <> masterParser.io.sram_r
      lvdsSMDeq(1)    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
      smUnit(5).io.sram_r <> masterParser.io.sram_r
      lvdsSMDeq(2)    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
      smUnit(7).io.sram_r <> masterParser.io.sram_r
      lvdsSMDeq(3)    := masterParser.io.txDeq
    }



    interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
    interface.io.intMstTrig(0) := masterParser.io.txDeq
    interface.io.intMstTrig(1) := masterParser.io.rxEnq

    interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
    interface.io.upRecStat   := masterParser.io.upRecStat

  }

  masterParser.io.req         := interface.io.txReq.valid
  // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength

  // io.rsp := masterParser.io.rsp

  masterParser.io.cReg := interface.io.cReg
  masterParser.io.mReg := interface.io.mReg

  
}


trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>

  when( interface.io.cReg.modeSel === false.B ){
    slaveParser.io.downIn  <> downCDRInAxis.io.axis
    downCDROut.io.axis <> slaveParser.io.downOut
    slaveParser.io.upIn    <> upCDRInAxis.io.axis
    upCDROut.io.axis   <> slaveParser.io.upOut
  }

  slaveParser.io.cReg := interface.io.cReg
  slaveParser.io.sReg := interface.io.sReg

  when( interface.io.cReg.modeSel === false.B ){
    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)

    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)

    lvdsSMEnq(0) := slaveParser.io.dSMenq(0)
    lvdsSMEnq(1) := slaveParser.io.dSMenq(1)
    lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
    lvdsSMEnq(3) := slaveParser.io.dSMenq(3)

    lvdsSMComf(0) := slaveParser.io.downRecStat.isFinish
    lvdsSMComf(1) := slaveParser.io.downRecStat.isFinish
    lvdsSMComf(2) := slaveParser.io.downRecStat.isFinish
    lvdsSMComf(3) := slaveParser.io.downRecStat.isFinish

    lvdsSMAbrt(0) := slaveParser.io.downRecStat.isRecError
    lvdsSMAbrt(1) := slaveParser.io.downRecStat.isRecError
    lvdsSMAbrt(2) := slaveParser.io.downRecStat.isRecError
    lvdsSMAbrt(3) := slaveParser.io.downRecStat.isRecError

    lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
    lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
    lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
    lvdsSMDeq(3) := slaveParser.io.uSMdeq(3)

    interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
    interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime
    interface.io.deltaFinal   := slaveParser.io.deltaFinal

    interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0)
    interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0)
    interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1)
    interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1)
    interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2)
    interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2)
    interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3)
    interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3)

    interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0)
    interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1)


    interface.io.downRecStat := slaveParser.io.downRecStat
    interface.io.upRecStat   := slaveParser.io.upRecStat

  }

  slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
  slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
  downCDRInAxis.io.flush  := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
  upCDRInAxis.io.flush    := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
  downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
  upCDROut.io.flush   := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )

  interface.io.lvds <> slaveParser.io.lvds

  interface.io.localDevIndex := slaveParser.io.localDevIndex

  //从站链路寄存器
  // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
  // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
  // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
  interface.io.isDevOnRight := slaveParser.io.isDevOnRight
  interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
  interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
}


trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>

  //看门狗1~16，SM监控
  val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
  val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }

  for( i <- 0 until 8 ){
    when( smUnit(i).io.enq ){
      isWdtSMEnable(2*i) := false.B
    } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){
      isWdtSMEnable(2*i) := true.B
    }

    when( smUnit(i).io.deq ){
      isWdtSMEnable(2*i + 1) := false.B
    } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){
      isWdtSMEnable(2*i + 1) := true.B
    }
  }

  for( i <- 0 until 16 ){
    when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){
      wdtSMCnt(i) := wdtSMCnt(i) + 1.U
    } .elsewhen( ~isWdtSMEnable(i) || (wdtSMCnt(i) >= interface.io.cReg.wdtTarCnt(i+1)) ){
      wdtSMCnt(i) := 0.U
    }

    // assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" )
    
    interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
  }

  //看门狗0 发送后回包是否超时
  val isWdtRec2RtnEnable = RegInit(false.B)
  val wdtRec2RtnCnt = RegInit(0.U(32.W))

  when( 
    (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) |
    ~interface.io.cReg.wdtEnable.extract(0)
  ){
    isWdtRec2RtnEnable := false.B
  } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
    isWdtRec2RtnEnable := true.B
  }

  when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){
    wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U
  } .elsewhen( ~isWdtRec2RtnEnable || (wdtRec2RtnCnt >= interface.io.cReg.wdtTarCnt(0)) ){
    wdtRec2RtnCnt := 0.U
  }

  // assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" )

  interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)

  //看门狗17
  val wdtRec2RecCnt = RegInit(0.U(32.W))

  when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
    wdtRec2RecCnt := wdtRec2RecCnt + 1.U
  } .elsewhen(
    ~interface.io.cReg.wdtEnable.extract(17) ||
    downCDRInAxis.io.axis.fire || 
    (wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17))
  ){
    wdtRec2RecCnt := 0.U
  }

  interface.io.wdtTrigger(17) := wdtRec2RecCnt === interface.io.cReg.wdtTarCnt(17)

}

trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
  val isDwUpEx = interface.io.cReg.dwupEx.extract(0)

  when( ~isDwUpEx ){ //未交叉
    when( interface.io.cReg.modeSel === false.B ){ //slave
      when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
        downInSerDat  := false.B
        upInSerDat  := false.B
        when( slaveParser.io.isLoop ){ //回环
          io.dDatOut := false.B
          io.uDatOut := io.dDatIn
        } .otherwise{ //非回环
          io.dDatOut := io.dDatIn
          io.uDatOut := io.uDatIn      
        }
      } .otherwise{ //无硬件错误
        when( slaveParser.io.isLoop ){ //回环
          downInSerDat  := io.dDatIn
          upInSerDat    := downCDROut.io.serDat
          io.dDatOut := false.B
          io.uDatOut := upCDROut.io.serDat 
        } .otherwise{ //非回环
          downInSerDat  := io.dDatIn
          upInSerDat    := io.uDatIn
          io.dDatOut := downCDROut.io.serDat
          io.uDatOut := upCDROut.io.serDat
        }
      }
    } .otherwise{ //master
      downInSerDat  := false.B
      upInSerDat    := io.uDatIn
      io.dDatOut := downCDROut.io.serDat
      io.uDatOut := false.B
    }
  } .otherwise{ //交叉
    when( interface.io.cReg.modeSel === false.B ){ //slave
      when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误

        when( slaveParser.io.isLoop ){ //回环
          io.dDatOut := io.uDatIn
          io.uDatOut := false.B
          downInSerDat  := false.B
          upInSerDat  := false.B
        } .otherwise{ //非回环
          io.dDatOut := io.dDatIn
          io.uDatOut := io.uDatIn   
          downInSerDat  := false.B
          upInSerDat  := false.B   
        }
      } .otherwise{ //无硬件错误
        when( slaveParser.io.isLoop ){ //回环
          downInSerDat  := io.uDatIn
          upInSerDat    := downCDROut.io.serDat
          io.uDatOut := false.B
          io.dDatOut := upCDROut.io.serDat 
        } .otherwise{ //非回环
          downInSerDat  := io.uDatIn
          upInSerDat    := io.dDatIn
          io.dDatOut := upCDROut.io.serDat
          io.uDatOut := downCDROut.io.serDat
        }
      }
    } .otherwise{ //master
      downInSerDat  := false.B
      upInSerDat    := io.dDatIn
      io.uDatOut := downCDROut.io.serDat
      io.dDatOut := false.B
    }
  }
}

trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
  val isUsing8b10b = interface.io.cReg.b8b4Sel.extract(0)

  when( isUsing8b10b ){
    b8b10DownEncoder.io <> downCDROut.io.encode
    b8b10DownDecoder.io <> downCDRInAxis.io.decode
    b8b10UpEncoder.io   <> upCDROut.io.encode
    b8b10UpDecoder.io   <> upCDRInAxis.io.decode

    b4b5DownEncoder.io.isEnable := false.B
    b4b5DownEncoder.io.dataIn := 0.U
    b4b5DownDecoder.io.dataIn := 0.U
    b4b5UpEncoder.io.isEnable := false.B
    b4b5UpEncoder.io.dataIn := 0.U
    b4b5UpDecoder.io.dataIn := 0.U
  } .otherwise{
    b4b5DownEncoder.io <> downCDROut.io.encode
    b4b5DownDecoder.io <> downCDRInAxis.io.decode
    b4b5UpEncoder.io <> upCDROut.io.encode
    b4b5UpDecoder.io <> upCDRInAxis.io.decode

    b8b10DownEncoder.io.isEnable := false.B
    b8b10DownEncoder.io.dataIn := 0.U
    b8b10DownDecoder.io.dataIn := 0.U
    b8b10UpEncoder.io.isEnable := false.B
    b8b10UpEncoder.io.dataIn := 0.U
    b8b10UpDecoder.io.dataIn := 0.U
  }
}

trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
  val cdrSelB = interface.io.cReg.cdrParam === 1.U
  val cdrSelC = interface.io.cReg.cdrParam === 2.U
  val cdrSelA = ~cdrSelB & ~cdrSelC

  // val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
  // val upCDRSampleIn   = Vec(3, Flipped(new CDRInSampleIO) )




  when(cdrSelB){
    io.downCDRSampleIn(1).serDat := downInSerDat
    io.upCDRSampleIn(1).serDat   := downInSerDat
    downInSyncSerDat := io.downCDRSampleIn(1).syncSerDat
    upInSyncSerDat := io.upCDRSampleIn(1).syncSerDat
    
    io.downCDRSampleIn(0).serDat := false.B
    io.upCDRSampleIn(0).serDat   := false.B
    io.downCDRSampleIn(2).serDat := false.B
    io.upCDRSampleIn(2).serDat   := false.B
  } .elsewhen(cdrSelC){
    io.downCDRSampleIn(2).serDat := downInSerDat
    io.upCDRSampleIn(2).serDat   := downInSerDat
    downInSyncSerDat := io.downCDRSampleIn(2).syncSerDat
    upInSyncSerDat := io.upCDRSampleIn(2).syncSerDat

    io.downCDRSampleIn(0).serDat := false.B
    io.upCDRSampleIn(0).serDat   := false.B
    io.downCDRSampleIn(1).serDat := false.B
    io.upCDRSampleIn(1).serDat   := false.B
  } .otherwise{
    io.downCDRSampleIn(0).serDat := downInSerDat
    io.upCDRSampleIn(0).serDat   := downInSerDat
    downInSyncSerDat := io.downCDRSampleIn(0).syncSerDat
    upInSyncSerDat := io.upCDRSampleIn(0).syncSerDat

    io.downCDRSampleIn(1).serDat := false.B
    io.upCDRSampleIn(1).serDat   := false.B
    io.downCDRSampleIn(2).serDat := false.B
    io.upCDRSampleIn(2).serDat   := false.B
  }



}

class MstSlvSwitch extends MstSlvSwitchBase
with MstSlvSwitchMaster
with MstSlvSwitchSlave
with MstSlvSwitchWatchDog
with MstSlvSwitchDataPath
with MstSlvSwitchB8B4
with MstSlvSwitchCDRIn{










}